From 84c798d9e4955aba7b2304bd265303848ecd3d5e Mon Sep 17 00:00:00 2001
From: Matt Guthaus <mrg@ucsc.edu>
Date: Fri, 9 Feb 2018 10:29:37 -0800
Subject: [PATCH] Move last few modules to base dir

---
 compiler/{ => base}/lef.py     | 0
 compiler/{ => base}/route.py   | 0
 compiler/{ => base}/verilog.py | 0
 3 files changed, 0 insertions(+), 0 deletions(-)
 rename compiler/{ => base}/lef.py (100%)
 rename compiler/{ => base}/route.py (100%)
 rename compiler/{ => base}/verilog.py (100%)

diff --git a/compiler/lef.py b/compiler/base/lef.py
similarity index 100%
rename from compiler/lef.py
rename to compiler/base/lef.py
diff --git a/compiler/route.py b/compiler/base/route.py
similarity index 100%
rename from compiler/route.py
rename to compiler/base/route.py
diff --git a/compiler/verilog.py b/compiler/base/verilog.py
similarity index 100%
rename from compiler/verilog.py
rename to compiler/base/verilog.py