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Fixed issues with sen control logic for read ports.

This commit is contained in:
Hunter Nichols 2020-02-19 03:06:11 -08:00
parent 125bcafb3e
commit 843fce41d7
2 changed files with 2 additions and 2 deletions
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2
compiler/characterizer/delay.py
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@ -650,7 +650,7 @@ class delay(simulation):
debug.error("Timed out, could not find a feasible period.",2) debug.error("Timed out, could not find a feasible period.",2)
# Clear any write target ports and set read port # Clear any write target ports and set read port
self.targ_write_ports = [port] self.targ_write_ports = []
self.targ_read_ports = [port] self.targ_read_ports = [port]
debug.info(1, "Trying feasible period: {0}ns on Port {1}".format(feasible_period, port)) debug.info(1, "Trying feasible period: {0}ns on Port {1}".format(feasible_period, port))

2
compiler/modules/control_logic.py
View File

@ -647,7 +647,7 @@ class control_logic(design.design):
if self.port_type=="rw": if self.port_type=="rw":
input_name = "we_bar" input_name = "we_bar"
else: else:
input_name = "cs_bar" input_name = "cs"
# GATE FOR S_EN # GATE FOR S_EN
self.s_en_gate_inst = self.add_inst(name="buf_s_en_and", self.s_en_gate_inst = self.add_inst(name="buf_s_en_and",
mod=self.sen_and3) mod=self.sen_and3)