diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py
index 2a8d5293..94e38ff2 100644
--- a/compiler/characterizer/delay.py
+++ b/compiler/characterizer/delay.py
@@ -650,7 +650,7 @@ class delay(simulation):
                 debug.error("Timed out, could not find a feasible period.",2)
             
             # Clear any write target ports and set read port
-            self.targ_write_ports = [port]
+            self.targ_write_ports = []
             self.targ_read_ports = [port]
            
             debug.info(1, "Trying feasible period: {0}ns on Port {1}".format(feasible_period, port))
diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py
index e22d05b3..458b9b96 100644
--- a/compiler/modules/control_logic.py
+++ b/compiler/modules/control_logic.py
@@ -647,7 +647,7 @@ class control_logic(design.design):
         if self.port_type=="rw":
             input_name = "we_bar"
         else:
-            input_name = "cs_bar"
+            input_name = "cs"
         # GATE FOR S_EN
         self.s_en_gate_inst = self.add_inst(name="buf_s_en_and",
                                             mod=self.sen_and3)