Fixed issues with sen control logic for read ports.

2026-08-29 17:39:02 +02:00 · 2020-02-19 03:06:11 -08:00
parent 125bcafb3e
commit 843fce41d7
2 changed files with 2 additions and 2 deletions
@@ -647,7 +647,7 @@ class control_logic(design.design):
        if self.port_type=="rw":
            input_name = "we_bar"
        else:
-            input_name = "cs_bar"
+            input_name = "cs"
        # GATE FOR S_EN
        self.s_en_gate_inst = self.add_inst(name="buf_s_en_and",
                                            mod=self.sen_and3)