Fixed issues with sen control logic for read ports.

2026-09-04 00:40:09 +02:00 · 2020-02-19 03:06:11 -08:00
parent 125bcafb3e
commit 843fce41d7
2 changed files with 2 additions and 2 deletions
@@ -650,7 +650,7 @@ class delay(simulation):
                debug.error("Timed out, could not find a feasible period.",2)
            
            # Clear any write target ports and set read port
-            self.targ_write_ports = [port]
+            self.targ_write_ports = []
            self.targ_read_ports = [port]
           
            debug.info(1, "Trying feasible period: {0}ns on Port {1}".format(feasible_period, port))