From 82bbacdfb57b100a2fac521525a390a667ff2598 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 20 Jul 2020 13:43:57 -0700 Subject: [PATCH] Add data bus gap to dynamically computed channel width --- compiler/sram/sram_1bank.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py index f8c30428..2808c8ca 100644 --- a/compiler/sram/sram_1bank.py +++ b/compiler/sram/sram_1bank.py @@ -465,7 +465,7 @@ class sram_1bank(sram_base): self.add_inst("hc", cr) self.connect_inst([]) else: - self.data_bus_size[port] = max(cr.height, self.col_addr_bus_size[port]) + self.data_bus_size[port] = max(cr.height, self.col_addr_bus_size[port]) + self.data_bus_gap else: offset = vector(0, self.bank.height + 2 * self.m1_space) @@ -477,7 +477,7 @@ class sram_1bank(sram_base): self.add_inst("hc", cr) self.connect_inst([]) else: - self.data_bus_size[port] = max(cr.height, self.col_addr_bus_size[port]) + self.data_bus_size[port] = max(cr.height, self.col_addr_bus_size[port]) + self.data_bus_gap def route_clk(self): """ Route the clock network """