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col_mux.py update with correct contacts

This commit is contained in:
Joey Kunzler 2020-04-20 22:08:29 -07:00
parent 63bea67fb5
commit 829f3e03fa
1 changed files with 28 additions and 1 deletions
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29
compiler/pgates/single_level_column_mux.py
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@ -57,7 +57,10 @@ class single_level_column_mux(pgate.pgate):
# Adds nmos_lower,nmos_upper to the module # Adds nmos_lower,nmos_upper to the module
self.ptx_width = self.tx_size * drc("minwidth_tx") self.ptx_width = self.tx_size * drc("minwidth_tx")
self.nmos = factory.create(module_type="ptx", width=self.ptx_width) self.nmos = factory.create(module_type="ptx",
width=self.ptx_width,
add_source_contact=False,
add_drain_contact=False)
self.add_mod(self.nmos) self.add_mod(self.nmos)
def add_pins(self): def add_pins(self):
@ -153,6 +156,30 @@ class single_level_column_mux(pgate.pgate):
offset=nmos_lower_d_pin.center(), offset=nmos_lower_d_pin.center(),
directions=("V", "V")) directions=("V", "V"))
# Add diffusion contacts
# These were previously omitted with the options: add_source_contact=False, add_drain_contact=False
# They are added now and not previously due to a s8 tech special case in which the contacts intersected the mux intraconnect
self.add_via_center(layers=self.active_stack,
offset=nmos_upper_d_pin.center(),
directions=("V", "V"),
implant_type="n",
well_type="nwell")
self.add_via_center(layers=self.active_stack,
offset=nmos_lower_s_pin.center(),
directions=("V", "V"),
implant_type="n",
well_type="nwell")
self.add_via_center(layers=self.active_stack,
offset=nmos_upper_s_pin.center(),
directions=("V", "V"),
implant_type="n",
well_type="nwell")
self.add_via_center(layers=self.active_stack,
offset=nmos_lower_d_pin.center(),
directions=("V", "V"),
implant_type="n",
well_type="nwell")
# bl -> nmos_upper/D on metal1 # bl -> nmos_upper/D on metal1
# bl_out -> nmos_upper/S on metal2 # bl_out -> nmos_upper/S on metal2
self.add_path(col_mux_stack[0], self.add_path(col_mux_stack[0],