luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Changed syntax in replica_bl tests, golden data to fit new values in delay tests.

This commit is contained in:
Hunter Nichols 2018-11-19 16:51:43 -08:00
parent e8f1c19af6
commit 8257e4fe8c
5 changed files with 45 additions and 46 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
compiler/characterizer/delay.py
View File

@ -429,7 +429,6 @@ class delay(simulation):
debug.info(2, "Check delay values for port {}".format(port)) debug.info(2, "Check delay values for port {}".format(port))
delay_names = [mname for mname in self.delay_meas_names] delay_names = [mname for mname in self.delay_meas_names]
delays = self.parse_values(delay_names, port, 1e9) # scale delays to ns delays = self.parse_values(delay_names, port, 1e9) # scale delays to ns
debug.info(2,"Delay values = {}".format(delays))
if not self.check_valid_delays(delays): if not self.check_valid_delays(delays):
return (False,{}) return (False,{})
result[port].update(delays) result[port].update(delays)

6
compiler/tests/14_replica_bitline_multiport_test.py
View File

@ -28,7 +28,7 @@ class replica_bitline_multiport_test(openram_test):
OPTS.num_w_ports = 0 OPTS.num_w_ports = 0
debug.info(2, "Testing 1rw 1r RBL with {0} FO4 stages, {1} rows".format(stages,rows)) debug.info(2, "Testing 1rw 1r RBL with {0} FO4 stages, {1} rows".format(stages,rows))
a = replica_bitline.replica_bitline(stages,fanout,rows) a = replica_bitline.replica_bitline(stages*[fanout],rows)
self.local_check(a) self.local_check(a)
# check replica bitline in pbitcell multi-port # check replica bitline in pbitcell multi-port
@ -39,7 +39,7 @@ class replica_bitline_multiport_test(openram_test):
OPTS.num_r_ports = 0 OPTS.num_r_ports = 0
debug.info(2, "Testing RBL pbitcell 1rw with {0} FO4 stages, {1} rows".format(stages,rows)) debug.info(2, "Testing RBL pbitcell 1rw with {0} FO4 stages, {1} rows".format(stages,rows))
a = replica_bitline.replica_bitline(stages,fanout,rows) a = replica_bitline.replica_bitline(stages*[fanout],rows)
self.local_check(a) self.local_check(a)
OPTS.num_rw_ports = 1 OPTS.num_rw_ports = 1
@ -47,7 +47,7 @@ class replica_bitline_multiport_test(openram_test):
OPTS.num_r_ports = 1 OPTS.num_r_ports = 1
debug.info(2, "Testing RBL pbitcell 1rw 1w 1r with {0} FO4 stages, {1} rows".format(stages,rows)) debug.info(2, "Testing RBL pbitcell 1rw 1w 1r with {0} FO4 stages, {1} rows".format(stages,rows))
a = replica_bitline.replica_bitline(stages,fanout,rows) a = replica_bitline.replica_bitline(stages*[fanout],rows)
self.local_check(a) self.local_check(a)
globals.end_openram() globals.end_openram()

4
compiler/tests/14_replica_bitline_test.py
View File

@ -22,14 +22,14 @@ class replica_bitline_test(openram_test):
fanout=4 fanout=4
rows=13 rows=13
debug.info(2, "Testing RBL with {0} FO4 stages, {1} rows".format(stages,rows)) debug.info(2, "Testing RBL with {0} FO4 stages, {1} rows".format(stages,rows))
a = replica_bitline.replica_bitline(stages,fanout,rows) a = replica_bitline.replica_bitline(stages*[fanout],rows)
self.local_check(a) self.local_check(a)
#debug.error("Exiting...", 1) #debug.error("Exiting...", 1)
stages=8 stages=8
rows=100 rows=100
debug.info(2, "Testing RBL with {0} FO4 stages, {1} rows".format(stages,rows)) debug.info(2, "Testing RBL with {0} FO4 stages, {1} rows".format(stages,rows))
a = replica_bitline.replica_bitline(stages,fanout,rows) a = replica_bitline.replica_bitline(stages*[fanout],rows)
self.local_check(a) self.local_check(a)

40
compiler/tests/21_hspice_delay_test.py
View File

@ -51,27 +51,27 @@ class timing_sram_test(openram_test):
#Assumes single rw port (6t sram) #Assumes single rw port (6t sram)
if OPTS.tech_name == "freepdk45": if OPTS.tech_name == "freepdk45":
golden_data = {'delay_hl': [2.5829000000000004], golden_data = {'delay_hl': [0.15801],
'delay_lh': [0.2255964], 'delay_lh': [0.15801],
'leakage_power': 0.0019498999999999996, 'leakage_power': 0.0023949,
'min_period': 4.844, 'min_period': 0.41,
'read0_power': [0.055371399999999994], 'read0_power': [0.628],
'read1_power': [0.0520225], 'read1_power': [0.60328],
'slew_hl': [0.0794261], 'slew_hl': [0.092516],
'slew_lh': [0.0236264], 'slew_lh': [0.092516],
'write0_power': [0.06545659999999999], 'write0_power': [0.7510600000000001],
'write1_power': [0.057846299999999996]} 'write1_power': [0.66619]}
elif OPTS.tech_name == "scn4m_subm": elif OPTS.tech_name == "scn4m_subm":
golden_data = {'delay_hl': [3.452], golden_data = {'delay_hl': [1.2],
'delay_lh': [1.3792000000000002], 'delay_lh': [1.2],
'leakage_power': 0.0257065, 'leakage_power': 0.026912,
'min_period': 4.688, 'min_period': 2.891,
'read0_power': [15.0755], 'read0_power': [24.7996],
'read1_power': [14.4526], 'read1_power': [23.9464],
'slew_hl': [0.6137363], 'slew_hl': [0.7045815],
'slew_lh': [0.3381045], 'slew_lh': [0.7045815],
'write0_power': [16.9203], 'write0_power': [27.8985],
'write1_power': [15.367]} 'write1_power': [25.1812]}
else: else:
self.assertTrue(False) # other techs fail self.assertTrue(False) # other techs fail
# Check if no too many or too few results # Check if no too many or too few results

40
compiler/tests/21_ngspice_delay_test.py
View File

@ -50,27 +50,27 @@ class timing_sram_test(openram_test):
data.update(port_data[0]) data.update(port_data[0])
if OPTS.tech_name == "freepdk45": if OPTS.tech_name == "freepdk45":
golden_data = {'delay_hl': [2.584251], golden_data = {'delay_hl': [0.16119519999999998],
'delay_lh': [0.22870469999999998], 'delay_lh': [0.16119519999999998],
'leakage_power': 0.0009567935, 'leakage_power': 0.01728358,
'min_period': 4.844, 'min_period': 0.469,
'read0_power': [0.0547588], 'read0_power': [0.5486122],
'read1_power': [0.051159970000000006], 'read1_power': [0.5276639000000001],
'slew_hl': [0.08164099999999999], 'slew_hl': [0.09102138],
'slew_lh': [0.025474979999999998], 'slew_lh': [0.09102138],
'write0_power': [0.06513271999999999], 'write0_power': [0.6586793],
'write1_power': [0.058057000000000004]} 'write1_power': [0.5893689999999999]}
elif OPTS.tech_name == "scn4m_subm": elif OPTS.tech_name == "scn4m_subm":
golden_data = {'delay_hl': [3.644147], golden_data = {'delay_hl': [1.342843],
'delay_lh': [1.629815], 'delay_lh': [1.342843],
'leakage_power': 0.001542964, 'leakage_power': 0.001683033,
'min_period': 4.688, 'min_period': 3.906,
'read0_power': [16.28732], 'read0_power': [19.55096],
'read1_power': [15.75155], 'read1_power': [18.99015],
'slew_hl': [0.6722473], 'slew_hl': [0.7687596],
'slew_lh': [0.3386347], 'slew_lh': [0.7687596],
'write0_power': [18.545450000000002], 'write0_power': [22.285880000000002],
'write1_power': [16.81084]} 'write1_power': [19.97167]}
else: else:
self.assertTrue(False) # other techs fail self.assertTrue(False) # other techs fail