From 8257e4fe8cc3ea1a65ddf3a38003907891ffb93a Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Mon, 19 Nov 2018 16:51:43 -0800 Subject: [PATCH] Changed syntax in replica_bl tests, golden data to fit new values in delay tests. --- compiler/characterizer/delay.py | 1 - .../14_replica_bitline_multiport_test.py | 6 +-- compiler/tests/14_replica_bitline_test.py | 4 +- compiler/tests/21_hspice_delay_test.py | 40 +++++++++---------- compiler/tests/21_ngspice_delay_test.py | 40 +++++++++---------- 5 files changed, 45 insertions(+), 46 deletions(-) diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index 1f0b37fb..f7fcfbd4 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -429,7 +429,6 @@ class delay(simulation): debug.info(2, "Check delay values for port {}".format(port)) delay_names = [mname for mname in self.delay_meas_names] delays = self.parse_values(delay_names, port, 1e9) # scale delays to ns - debug.info(2,"Delay values = {}".format(delays)) if not self.check_valid_delays(delays): return (False,{}) result[port].update(delays) diff --git a/compiler/tests/14_replica_bitline_multiport_test.py b/compiler/tests/14_replica_bitline_multiport_test.py index 55e3e8f0..41c3aa51 100755 --- a/compiler/tests/14_replica_bitline_multiport_test.py +++ b/compiler/tests/14_replica_bitline_multiport_test.py @@ -28,7 +28,7 @@ class replica_bitline_multiport_test(openram_test): OPTS.num_w_ports = 0 debug.info(2, "Testing 1rw 1r RBL with {0} FO4 stages, {1} rows".format(stages,rows)) - a = replica_bitline.replica_bitline(stages,fanout,rows) + a = replica_bitline.replica_bitline(stages*[fanout],rows) self.local_check(a) # check replica bitline in pbitcell multi-port @@ -39,7 +39,7 @@ class replica_bitline_multiport_test(openram_test): OPTS.num_r_ports = 0 debug.info(2, "Testing RBL pbitcell 1rw with {0} FO4 stages, {1} rows".format(stages,rows)) - a = replica_bitline.replica_bitline(stages,fanout,rows) + a = replica_bitline.replica_bitline(stages*[fanout],rows) self.local_check(a) OPTS.num_rw_ports = 1 @@ -47,7 +47,7 @@ class replica_bitline_multiport_test(openram_test): OPTS.num_r_ports = 1 debug.info(2, "Testing RBL pbitcell 1rw 1w 1r with {0} FO4 stages, {1} rows".format(stages,rows)) - a = replica_bitline.replica_bitline(stages,fanout,rows) + a = replica_bitline.replica_bitline(stages*[fanout],rows) self.local_check(a) globals.end_openram() diff --git a/compiler/tests/14_replica_bitline_test.py b/compiler/tests/14_replica_bitline_test.py index 9efd3eec..94a49f55 100755 --- a/compiler/tests/14_replica_bitline_test.py +++ b/compiler/tests/14_replica_bitline_test.py @@ -22,14 +22,14 @@ class replica_bitline_test(openram_test): fanout=4 rows=13 debug.info(2, "Testing RBL with {0} FO4 stages, {1} rows".format(stages,rows)) - a = replica_bitline.replica_bitline(stages,fanout,rows) + a = replica_bitline.replica_bitline(stages*[fanout],rows) self.local_check(a) #debug.error("Exiting...", 1) stages=8 rows=100 debug.info(2, "Testing RBL with {0} FO4 stages, {1} rows".format(stages,rows)) - a = replica_bitline.replica_bitline(stages,fanout,rows) + a = replica_bitline.replica_bitline(stages*[fanout],rows) self.local_check(a) diff --git a/compiler/tests/21_hspice_delay_test.py b/compiler/tests/21_hspice_delay_test.py index 5facb482..033cfbb6 100755 --- a/compiler/tests/21_hspice_delay_test.py +++ b/compiler/tests/21_hspice_delay_test.py @@ -51,27 +51,27 @@ class timing_sram_test(openram_test): #Assumes single rw port (6t sram) if OPTS.tech_name == "freepdk45": - golden_data = {'delay_hl': [2.5829000000000004], - 'delay_lh': [0.2255964], - 'leakage_power': 0.0019498999999999996, - 'min_period': 4.844, - 'read0_power': [0.055371399999999994], - 'read1_power': [0.0520225], - 'slew_hl': [0.0794261], - 'slew_lh': [0.0236264], - 'write0_power': [0.06545659999999999], - 'write1_power': [0.057846299999999996]} + golden_data = {'delay_hl': [0.15801], + 'delay_lh': [0.15801], + 'leakage_power': 0.0023949, + 'min_period': 0.41, + 'read0_power': [0.628], + 'read1_power': [0.60328], + 'slew_hl': [0.092516], + 'slew_lh': [0.092516], + 'write0_power': [0.7510600000000001], + 'write1_power': [0.66619]} elif OPTS.tech_name == "scn4m_subm": - golden_data = {'delay_hl': [3.452], - 'delay_lh': [1.3792000000000002], - 'leakage_power': 0.0257065, - 'min_period': 4.688, - 'read0_power': [15.0755], - 'read1_power': [14.4526], - 'slew_hl': [0.6137363], - 'slew_lh': [0.3381045], - 'write0_power': [16.9203], - 'write1_power': [15.367]} + golden_data = {'delay_hl': [1.2], + 'delay_lh': [1.2], + 'leakage_power': 0.026912, + 'min_period': 2.891, + 'read0_power': [24.7996], + 'read1_power': [23.9464], + 'slew_hl': [0.7045815], + 'slew_lh': [0.7045815], + 'write0_power': [27.8985], + 'write1_power': [25.1812]} else: self.assertTrue(False) # other techs fail # Check if no too many or too few results diff --git a/compiler/tests/21_ngspice_delay_test.py b/compiler/tests/21_ngspice_delay_test.py index e203b878..b0275c1c 100755 --- a/compiler/tests/21_ngspice_delay_test.py +++ b/compiler/tests/21_ngspice_delay_test.py @@ -50,27 +50,27 @@ class timing_sram_test(openram_test): data.update(port_data[0]) if OPTS.tech_name == "freepdk45": - golden_data = {'delay_hl': [2.584251], - 'delay_lh': [0.22870469999999998], - 'leakage_power': 0.0009567935, - 'min_period': 4.844, - 'read0_power': [0.0547588], - 'read1_power': [0.051159970000000006], - 'slew_hl': [0.08164099999999999], - 'slew_lh': [0.025474979999999998], - 'write0_power': [0.06513271999999999], - 'write1_power': [0.058057000000000004]} + golden_data = {'delay_hl': [0.16119519999999998], + 'delay_lh': [0.16119519999999998], + 'leakage_power': 0.01728358, + 'min_period': 0.469, + 'read0_power': [0.5486122], + 'read1_power': [0.5276639000000001], + 'slew_hl': [0.09102138], + 'slew_lh': [0.09102138], + 'write0_power': [0.6586793], + 'write1_power': [0.5893689999999999]} elif OPTS.tech_name == "scn4m_subm": - golden_data = {'delay_hl': [3.644147], - 'delay_lh': [1.629815], - 'leakage_power': 0.001542964, - 'min_period': 4.688, - 'read0_power': [16.28732], - 'read1_power': [15.75155], - 'slew_hl': [0.6722473], - 'slew_lh': [0.3386347], - 'write0_power': [18.545450000000002], - 'write1_power': [16.81084]} + golden_data = {'delay_hl': [1.342843], + 'delay_lh': [1.342843], + 'leakage_power': 0.001683033, + 'min_period': 3.906, + 'read0_power': [19.55096], + 'read1_power': [18.99015], + 'slew_hl': [0.7687596], + 'slew_lh': [0.7687596], + 'write0_power': [22.285880000000002], + 'write1_power': [19.97167]} else: self.assertTrue(False) # other techs fail