mirror of https://github.com/VLSIDA/OpenRAM.git
Recover function for measures
This commit is contained in:
Bugra Onal
parent
6603220258
commit
816eff711d
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@ -17,6 +17,8 @@ from .bit_polarity import *
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from globals import OPTS
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from .simulation import simulation
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from .measurements import *
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from os import path
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import re
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class delay(simulation):
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@ -118,8 +120,10 @@ class delay(simulation):
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# Other measurements associated with the read port not included in the liberty file
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read_measures.append(self.create_bitline_measurement_objects())
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read_measures.append(self.create_debug_measurement_objects())
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read_measures.append(self.create_read_bit_measures())
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read_measures.append(self.create_sen_and_bitline_path_measures())
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# TODO: Maybe don't do this here (?)
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if OPTS.top_process != "memchar":
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read_measures.append(self.create_read_bit_measures())
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read_measures.append(self.create_sen_and_bitline_path_measures())
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return read_measures
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@ -245,8 +249,8 @@ class delay(simulation):
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def create_sen_and_bitline_path_measures(self):
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"""Create measurements for the s_en and bitline paths for individual delays per stage."""
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# FIXME: There should be a default_read_port variable in this case, pathing is done with this
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# but is never mentioned otherwise
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# # FIXME: There should be a default_read_port variable in this case, pathing is done with this
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# # but is never mentioned otherwise
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port = self.read_ports[0]
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sen_and_port = self.sen_name + str(port)
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bl_and_port = self.bl_name.format(port) # bl_name contains a '{}' for the port
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@ -391,12 +395,12 @@ class delay(simulation):
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# creates and opens stimulus file for writing
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self.delay_stim_sp = "delay_stim.sp"
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temp_stim = "{0}/{1}".format(self.output_path, self.delay_stim_sp)
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temp_stim = path.join(self.output_path, self.delay_stim_sp)
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self.sf = open(temp_stim, "w")
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# creates and opens measure file for writing
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self.delay_meas_sp = "delay_meas.sp"
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temp_meas = "{0}/{1}".format(self.output_path, self.delay_meas_sp)
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temp_meas = path.join(self.output_path, self.delay_meas_sp)
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self.mf = open(temp_meas, "w")
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if OPTS.spice_name == "spectre":
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@ -429,7 +433,7 @@ class delay(simulation):
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t_rise=self.slew,
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t_fall=self.slew)
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self.stim.write_include(temp_meas)
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self.sf.write(".include {0}".format(temp_meas))
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# self.load_all_measure_nets()
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self.write_delay_measures()
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# self.write_simulation_saves()
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@ -448,15 +452,15 @@ class delay(simulation):
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# creates and opens stimulus file for writing
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self.power_stim_sp = "power_stim.sp"
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temp_stim = "{0}/{1}".format(self.output_path, self.power_stim_sp)
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temp_stim = path.join(self.output_path, self.power_stim_sp)
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self.sf = open(temp_stim, "w")
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self.sf.write("* Power stimulus for period of {0}n\n\n".format(self.period))
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self.stim = stimuli(self.sf, self.corner)
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# creates and opens measure file for writing
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self.power_meas_sp = "power_meas.sp"
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temp_meas = "{0}/{1}".format(opts.openram_temp, self.power_meas_sp)
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temp_meas = path.join(self.output_path, self.power_meas_sp)
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self.mf = open(temp_meas, "w")
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self.stim = stimuli(self.sf, self.mf, self.corner)
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# include UNTRIMMED files in stimulus file
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if trim:
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@ -488,7 +492,7 @@ class delay(simulation):
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for port in self.all_ports:
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self.stim.gen_constant(sig_name="CLK{0}".format(port), v_val=0)
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self.stim.write_include(temp_meas)
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self.sf.write(".include {}".format(temp_meas))
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self.write_power_measures()
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# run until the end of the cycle time
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@ -1151,15 +1155,90 @@ class delay(simulation):
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if self.sp_file != self.sim_sp_file:
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shutil.copy(self.sp_file, self.sim_sp_file)
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def recover_measurment_objects(self):
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mf = open(path.join(OPTS.output_path, "delay_meas.sp"), "r")
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measure_text = mf.read()
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port_iter = re.finditer(r"\* (Read|Write) ports (\d*)", measure_text)
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port_measure_lines = []
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loc = 0
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port_name = ''
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for port in port_iter:
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port_measure_lines.append((port_name, measure_txt[loc:port.end(0)]))
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loc = port.start(0)
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port_name = port.group(1) + port.group(2)
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mf.close()
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# Cycle comments, not sure if i need this
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cycle_lines = port_measure_lines.pop(0)[1]
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# For now just recover the bit_measures and sen_and_bitline_path_measures
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self.read_meas_lists.append([])
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bit_measure_rule = re.compile(r"\.meas tran (v_q_a\d+_b\d+_(read|write)_(zero|one)\d+) FIND v\((.*)\) AT=(\d+(\.\d+)?)n")
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for measures in port_measure_lines:
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port_name = measures[0]
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text = measures[1]
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bit_measure_iter = bit_measure_rule.finditer(text)
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for bit_measure in bit_measure_iter:
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meas_name = bit_measure.group(1)
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read = bit_measure.group(2) == "read"
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probe = bit_measure.group(4)
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polarity = bit_polarity.NONINVERTING
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if "q_bar" in meas_name:
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polarity = bit_polarity.INVERTING
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meas = voltage_at_measure(meas_name, probe)
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if read:
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self.read_bit_meas[polarity].append(meas)
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self.read_meas_lists[-1].append(meas)
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else:
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self.write_bit_meas[polarity].append(meas)
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self.write_meas_lists[-1].append(meas)
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delay_path_rule = re.compile(r"\.meas tran delay_(.*)_to_(.*) TRIG v\((.*)\) VAL=(\d+(\.\d+)?) (RISE|FALL)=(\d+) TD=(\d+(\.\d+)?)n TARG v\((.*)\) VAL=(\d+(\.\d+)?) (RISE|FALL)=(\d+) TD=(\d+(\.\d+)?)n")
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port = self.read_ports[0]
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sen_and_port = self.sen_name + str(port)
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bl_and_port = self.bl_name.format(port) # bl_name contains a '{}' for the port
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meas_buff = []
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for measures in port_measure_lines:
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port_name = measures[0]
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text = measures[1]
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delay_path_iter = delay_path_rule.finditer(text)
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for delay_path_measure in delay_path_iter:
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from_ = delay_path_measure.group(1)
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to_ = delay_path_measure.group(2)
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trig_rise = delay_path_measure.group(5)
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targ_rise = delay_path_measure.group(10)
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meas_name = "delay_{0}_to_{1}".format(from_, to_)
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meas = delay_measure(meas_name, from_, to_, trig_rise, targ_rise, measure_scale=1e9, has_port=False)
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meas.meta_str = sram_op.READ_ZERO
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meas.meta_add_delay = True
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meas_buff.append(meas)
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# TODO: we are losing duplicate measures here
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if from_ == sen_and_port:
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self.sen_path_meas.extend(meas_buff.copy())
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meas_buff.clear()
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elif from_ == bl_and_port:
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self.bl_path_meas.extend(meas_buff)
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meas_buff.clear()
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self.read_meas_lists.append(self.sen_path_meas + self.bl_path_meas)
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def analysis_init(self, probe_address, probe_data):
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"""Sets values which are dependent on the data address/bit being tested."""
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self.set_probe(probe_address, probe_data)
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self.prepare_netlist()
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self.create_graph()
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self.set_internal_spice_names()
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self.create_measurement_names()
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self.create_measurement_objects()
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if OPTS.top_process == "memchar":
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# TODO: fix
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self.bl_name = "xsram.xbank0.bl_0_{}"
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self.br_name = "xsram.xbank0.br_0_{}"
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self.sen_name = "xsram.s_en"
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self.create_measurement_objects()
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self.recover_measurment_objects()
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else:
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self.create_graph()
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self.set_internal_spice_names()
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self.create_measurement_names()
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self.create_measurement_objects()
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def analyze(self, probe_address, probe_data, load_slews):
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"""
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@ -10,9 +10,14 @@ class fake_sram(sram_config):
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"""
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def __init__(self, name, word_size, num_words, write_size=None, num_banks=1,
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words_per_row=None, num_spare_rows=0, num_spare_cols=0):
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sram_config.__init__(self, name, word_size, num_words, write_size=None,
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num_banks=1, words_per_row=None, num_spare_rows=0,
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num_spare_cols=0)
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sram_config.__init__(self, word_size, num_words, write_size,
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num_banks, words_per_row, num_spare_rows,
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num_spare_cols)
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self.name = name
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if write_size and self.write_size != self.word_size:
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self.num_wmasks = int(ceil(self.word_size / self.write_size))
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else:
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self.num_wmasks = 0
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def setup_multiport_constants(self):
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"""
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@ -88,35 +93,36 @@ class fake_sram(sram_config):
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self.pins.extend(['clk{}'.format(port) for port in range(
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self.num_rw_ports + self.num_r_ports + self.num_w_ports)])
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for port in range(self.num_rw_ports):
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self.pins.extend(['din{0}[{1}]]'.format(port, bit)
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self.pins.extend(['din{0}[{1}]'.format(port, bit)
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for bit in range(self.num_cols)])
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self.pins.extend(['dout{0}[{1}]]'.format(port, bit)
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self.pins.extend(['dout{0}[{1}]'.format(port, bit)
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for bit in range(self.num_cols)])
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self.pins.extend(['addr{0}[{1}]]'.format(port, bit)
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self.pins.extend(['addr{0}[{1}]'.format(port, bit)
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for bit in range(self.addr_size)])
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if self.num_wmasks != 0:
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self.pins.extend(['wmask{0}[{1}]]'.format(port, bit)
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print(self.num_wmasks)
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self.pins.extend(['wmask{0}[{1}]'.format(port, bit)
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for bit in range(self.num_wmasks)])
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self.pins.extend(['csb{}'.format(port), 'web{}'.format(port)])
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start_port = self.num_rw_ports
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for port in range(start_port, start_port + self.num_r_ports):
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self.pins.extend(['dout{0}[{1}]]'.format(port, bit)
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self.pins.extend(['dout{0}[{1}]'.format(port, bit)
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for bit in range(self.num_cols)])
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self.pins.extend(['addr{0}[{1}]]'.format(port, bit)
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self.pins.extend(['addr{0}[{1}]'.format(port, bit)
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for bit in range(self.addr_size)])
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self.pins.extend(['csb{}'.format(port)])
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start_port += self.num_r_ports
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for port in range(start_port, start_port + self.num_w_ports):
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self.pins.extend(['din{0}[{1}]]'.format(port, bit)
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self.pins.extend(['din{0}[{1}]'.format(port, bit)
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for bit in range(self.num_cols)])
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self.pins.extend(['addr{0}[{1}]]'.format(port, bit)
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self.pins.extend(['addr{0}[{1}]'.format(port, bit)
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for bit in range(self.addr_size)])
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if self.num_wmasks != 0:
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self.pins.extend(['wmask{0}[{1}]]'.format(port, bit)
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self.pins.extend(['wmask{0}[{1}]'.format(port, bit)
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for bit in range(self.num_wmasks)])
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self.pins.extend(['csb{}'.format(port), 'web{}'.format(port)])
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