mirror of https://github.com/VLSIDA/OpenRAM.git
Fake sram using sram class as base
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parent
2b79646b8f
commit
6603220258
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@ -0,0 +1,51 @@
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# This is a temp file. Remove either this or the fake_sram.py
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from modules import sram
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import debug
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from globals import OPTS
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import os
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class fake_sram_v2(sram):
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def create_netlist(self):
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# Make sure spice file is here
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debug.check(os.path.exists(self.sp_name), "Spice netlist in {} not found".format(self.sp_name))
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def generate_pins(self):
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self.pins = ['vdd', 'gnd']
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self.pins.extend(['clk{}'.format(port) for port in range(
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OPTS.num_rw_ports + OPTS.num_r_ports + OPTS.num_w_ports)])
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for port in range(OPTS.num_rw_ports):
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self.pins.extend(['din{0}[{1}]'.format(port, bit)
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for bit in range(self.num_cols)])
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self.pins.extend(['dout{0}[{1}]'.format(port, bit)
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for bit in range(self.num_cols)])
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self.pins.extend(['addr{0}[{1}]'.format(port, bit)
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for bit in range(self.addr_size)])
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#if self.num_wmasks != 0:
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# self.pins.extend(['wmask{0}[{1}]'.format(port, bit)
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# for bit in range(self.num_wmasks)])
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self.pins.extend(['csb{}'.format(port), 'web{}'.format(port)])
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start_port = OPTS.num_rw_ports
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for port in range(start_port, start_port + OPTS.num_r_ports):
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self.pins.extend(['dout{0}[{1}]'.format(port, bit)
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for bit in range(self.num_cols)])
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self.pins.extend(['addr{0}[{1}]'.format(port, bit)
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for bit in range(self.addr_size)])
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self.pins.extend(['csb{}'.format(port)])
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start_port += OPTS.num_r_ports
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for port in range(start_port, start_port + OPTS.num_w_ports):
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self.pins.extend(['din{0}[{1}]'.format(port, bit)
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for bit in range(self.num_cols)])
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self.pins.extend(['addr{0}[{1}]'.format(port, bit)
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for bit in range(self.addr_size)])
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if self.num_wmasks != 0:
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self.pins.extend(['wmask{0}[{1}]'.format(port, bit)
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for bit in range(self.num_wmasks)])
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self.pins.extend(['csb{}'.format(port), 'web{}'.format(port)])
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@ -39,19 +39,22 @@ init_openram(config_file=args[0], is_unit_test=False)
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print_banner()
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# Configure the SRAM organization (duplicated from openram.py)
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from characterizer.fake_sram import fake_sram
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s = fake_sram(name=OPTS.output_name,
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word_size=OPTS.word_size,
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num_words=OPTS.num_words,
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write_size=OPTS.write_size,
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num_banks=OPTS.num_banks,
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words_per_row=OPTS.words_per_row,
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num_spare_rows=OPTS.num_spare_rows,
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num_spare_cols=OPTS.num_spare_cols)
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#from characterizer.fake_sram import fake_sram
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from modules import sram_config
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from characterizer.fake_sram_v2 import fake_sram_v2
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config = sram_config(word_size=OPTS.word_size,
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num_words=OPTS.num_words,
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write_size=OPTS.write_size,
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num_banks=OPTS.num_banks,
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words_per_row=OPTS.words_per_row,
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num_spare_rows=OPTS.num_spare_rows,
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num_spare_cols=OPTS.num_spare_cols)
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s = fake_sram_v2(name=OPTS.output_name,
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sram_config=config)
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s.parse_html(args[1])
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#s.parse_html(args[1])
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s.generate_pins()
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s.setup_multiport_constants()
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#s.setup_multiport_constants()
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OPTS.netlist_only = True
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OPTS.check_lvsdrc = False
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@ -48,11 +48,9 @@ class sram():
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self.num_banks))
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start_time = datetime.datetime.now()
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self.name = name
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from .sram_1bank import sram_1bank as sram
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self.s = sram(name, sram_config)
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self.s = sram(self.name, self.config)
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self.s.create_netlist()
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if not OPTS.netlist_only:
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