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Merge branch 'dev' into multiport_characterization

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This commit is contained in:
Hunter Nichols
2019-02-26 22:48:39 -08:00
parent ea51cfdbb4 fa89e11f95
commit 816669b9ca
112 changed files with 794 additions and 24251 deletions
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technology/freepdk45/gds_lib/cell_1w_1r.gds
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technology/freepdk45/gds_lib/replica_cell_1w_1r.gds
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technology/freepdk45/sp_lib/cell_1w_1r.sp
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.SUBCKT cell_1w_1r bl0 br0 bl1 br1 wl0 wl1 vdd gnd
MM9 RA_to_R_right wl1 br1 gnd NMOS_VTG W=180.0n L=50n m=1
MM8 RA_to_R_right Q gnd gnd NMOS_VTG W=180.0n L=50n m=1
MM7 RA_to_R_left Q_bar gnd gnd NMOS_VTG W=180.0n L=50n m=1
MM6 RA_to_R_left wl1 bl1 gnd NMOS_VTG W=180.0n L=50n m=1
MM5 Q wl0 bl0 gnd NMOS_VTG W=135.00n L=50n m=1
MM4 Q_bar wl0 br0 gnd NMOS_VTG W=135.00n L=50n m=1
MM1 Q Q_bar gnd gnd NMOS_VTG W=205.0n L=50n m=1
MM0 Q_bar Q gnd gnd NMOS_VTG W=205.0n L=50n m=1
MM3 Q Q_bar vdd vdd PMOS_VTG W=90n L=50n m=1
MM2 Q_bar Q vdd vdd PMOS_VTG W=90n L=50n m=1
.ENDS
technology/freepdk45/sp_lib/replica_cell_1w_1r.sp
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.SUBCKT replica_cell_1w_1r bl0 br0 bl1 br1 wl0 wl1 vdd gnd
MM9 RA_to_R_right wl1 br1 gnd NMOS_VTG W=180.0n L=50n m=1
MM8 RA_to_R_right Q gnd gnd NMOS_VTG W=180.0n L=50n m=1
MM7 RA_to_R_left vdd gnd gnd NMOS_VTG W=180.0n L=50n m=1
MM6 RA_to_R_left wl1 bl1 gnd NMOS_VTG W=180.0n L=50n m=1
MM5 Q wl0 bl0 gnd NMOS_VTG W=135.00n L=50n m=1
MM4 vdd wl0 br0 gnd NMOS_VTG W=135.00n L=50n m=1
MM1 Q vdd gnd gnd NMOS_VTG W=205.0n L=50n m=1
MM0 vdd Q gnd gnd NMOS_VTG W=205.0n L=50n m=1
MM3 Q vdd vdd vdd PMOS_VTG W=90n L=50n m=1
MM2 vdd Q vdd vdd PMOS_VTG W=90n L=50n m=1
.ENDS
technology/scn4m_subm/gds_lib/cell_1w_1r.gds
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technology/scn4m_subm/gds_lib/replica_cell_1w_1r.gds
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technology/scn4m_subm/mag_lib/cell_6t.ext
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timestamp 1536091415
version 8.2
tech scmos
style TSMC0.35um(tsmc35)from:t11c
scale 1000 1 5
resistclasses 3700 2800 1018000 1018000 1 6000 6000 80 70 80 40
node "comment_0_0#" 0 0 0 0 bb 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
node "br" 6 -1.43219e-14 96 -8 ndc 320 72 0 0 0 0 0 0 0 0 0 0 0 0 512 96 3456 464 0 0 0 0
node "bl" 6 -8.88178e-16 40 -8 ndc 320 72 0 0 0 0 0 0 0 0 0 0 0 0 512 96 3200 432 0 0 0 0
node "wl" 115 -2.89546e-13 -8 12 p 0 0 0 0 0 0 0 0 0 0 1536 360 0 0 2496 344 0 0 0 0 0 0
node "a_36_40#" 140 -3.51719e-13 36 40 ndif 960 144 304 72 0 0 0 0 0 0 1984 424 0 0 2048 288 0 0 0 0 0 0
node "a_28_32#" 160 -8.06466e-13 28 32 p 960 144 304 72 0 0 0 0 0 0 2000 456 0 0 1920 272 0 0 0 0 0 0
node "gnd" 41 -27.888 -32 -32 pw 1792 240 512 128 0 0 0 0 29600 696 0 0 0 0 2688 400 6400 864 0 0 0 0
equiv "gnd" "gnd"
node "vdd" 2340 2596 -32 116 nw 256 64 800 176 17600 576 0 0 0 0 0 0 0 0 3456 464 256 64 0 0 0 0
cap "wl" "bl" 189.768
cap "a_36_40#" "br" 17.59
cap "wl" "br" 189.768
cap "vdd" "bl" 135.015
cap "bl" "br" 27.492
cap "vdd" "br" 117.084
cap "gnd" "a_28_32#" 880.405
cap "gnd" "a_36_40#" 401.284
cap "a_28_32#" "a_36_40#" 272.793
cap "gnd" "wl" 1198.41
cap "gnd" "bl" 712.11
cap "a_28_32#" "wl" 108.364
cap "vdd" "gnd" 510.12
cap "gnd" "br" 698.471
cap "a_36_40#" "wl" 108.364
cap "a_28_32#" "bl" 104.205
cap "vdd" "a_28_32#" 430.812
cap "a_36_40#" "bl" 29.396
cap "a_28_32#" "br" 308.488
cap "vdd" "a_36_40#" 709.108
fet nfet 96 12 97 13 128 48 "gnd" "wl" 16 0 "br" 16 0 "a_28_32#" 16 0
fet nfet 40 12 41 13 128 48 "gnd" "wl" 16 0 "bl" 16 0 "a_36_40#" 16 0
fet nfet 116 40 117 41 256 80 "gnd" "a_36_40#" 16 0 "a_28_32#" 32 0 "gnd" 32 0
fet nfet 28 40 29 41 256 80 "gnd" "a_28_32#" 16 0 "gnd" 32 0 "a_36_40#" 32 0
fet pfet 108 148 109 149 192 56 "vdd" "a_36_40#" 32 0 "a_28_32#" 12 0 "vdd" 12 0
fet pfet 28 148 29 149 192 56 "vdd" "a_28_32#" 32 0 "vdd" 12 0 "a_36_40#" 12 0
technology/scn4m_subm/mag_lib/cell_6t.spice
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* SPICE3 file created from cell_6t.ext - technology: scmos
M1000 a_36_40# a_28_32# vdd vdd pfet w=0.6u l=0.8u
+ ad=0.76p pd=3.6u as=2p ps=8.8u
M1001 vdd a_36_40# a_28_32# vdd pfet w=0.6u l=0.8u
+ ad=0p pd=0u as=0.76p ps=3.6u
M1002 a_36_40# a_28_32# gnd gnd nfet w=1.6u l=0.4u
+ ad=2.4p pd=7.2u as=4.48p ps=12u
M1003 gnd a_36_40# a_28_32# gnd nfet w=1.6u l=0.4u
+ ad=0p pd=0u as=2.4p ps=7.2u
M1004 a_36_40# wl bl gnd nfet w=0.8u l=0.4u
+ ad=0p pd=0u as=0.8p ps=3.6u
M1005 a_28_32# wl br gnd nfet w=0.8u l=0.4u
+ ad=0p pd=0u as=0.8p ps=3.6u
C0 vdd 0 2.60fF
technology/scn4m_subm/mag_lib/replica_cell_6t.ext
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timestamp 1541443051
version 8.2
tech scmos
style TSMC0.35um(tsmc35)from:t11c
scale 1000 1 5
resistclasses 3700 2800 1018000 1018000 1 6000 6000 80 70 80 40
node "comment_0_0#" 0 0 0 0 bb 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
node "br" 6 1.40998e-14 96 -8 ndc 320 72 0 0 0 0 0 0 0 0 0 0 0 0 512 96 3456 464 0 0 0 0
node "bl" 6 -8.88178e-16 40 -8 ndc 320 72 0 0 0 0 0 0 0 0 0 0 0 0 512 96 3200 432 0 0 0 0
node "wl" 115 -2.89546e-13 -8 12 p 0 0 0 0 0 0 0 0 0 0 1536 360 0 0 2496 344 0 0 0 0 0 0
node "a_36_40#" 140 -3.51719e-13 36 40 ndif 960 144 304 72 0 0 0 0 0 0 1984 424 0 0 2048 288 0 0 0 0 0 0
node "gnd" 41 -27.888 -32 -32 pw 1792 240 512 128 0 0 0 0 29600 696 0 0 0 0 2688 400 6400 864 0 0 0 0
equiv "gnd" "gnd"
node "vdd" 2517 2596 -32 116 nw 1216 208 1104 248 17600 576 0 0 0 0 2000 456 0 0 5632 736 256 64 0 0 0 0
cap "vdd" "br" 442.06
cap "bl" "wl" 189.768
cap "gnd" "br" 698.471
cap "bl" "a_36_40#" 29.396
cap "wl" "a_36_40#" 108.364
cap "bl" "vdd" 239.22
cap "bl" "gnd" 712.11
cap "wl" "vdd" 108.364
cap "wl" "gnd" 1198.41
cap "bl" "br" 27.492
cap "a_36_40#" "vdd" 981.901
cap "wl" "br" 189.768
cap "a_36_40#" "gnd" 401.284
cap "vdd" "gnd" 1390.52
cap "a_36_40#" "br" 17.59
fet nfet 96 12 97 13 128 48 "gnd" "wl" 16 0 "br" 16 0 "vdd" 16 0
fet nfet 40 12 41 13 128 48 "gnd" "wl" 16 0 "bl" 16 0 "a_36_40#" 16 0
fet nfet 116 40 117 41 256 80 "gnd" "a_36_40#" 16 0 "vdd" 32 0 "gnd" 32 0
fet nfet 28 40 29 41 256 80 "gnd" "vdd" 16 0 "gnd" 32 0 "a_36_40#" 32 0
fet pfet 108 148 109 149 192 56 "vdd" "a_36_40#" 32 0 "vdd" 24 0
fet pfet 28 148 29 149 192 56 "vdd" "vdd" 32 0 "vdd" 12 0 "a_36_40#" 12 0
technology/scn4m_subm/mag_lib/replica_cell_6t.spice
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* SPICE3 file created from replica_cell_6t.ext - technology: scmos
M1000 a_36_40# vdd vdd vdd pfet w=0.6u l=0.8u
+ ad=0.76p pd=3.6u as=2.76p ps=12.4u
** SOURCE/DRAIN TIED
M1001 vdd a_36_40# vdd vdd pfet w=0.8u l=0.6u
+ ad=0p pd=0u as=0p ps=0u
M1002 a_36_40# vdd gnd gnd nfet w=1.6u l=0.4u
+ ad=2.4p pd=7.2u as=4.48p ps=12u
M1003 gnd a_36_40# vdd gnd nfet w=1.6u l=0.4u
+ ad=0p pd=0u as=3.04p ps=10.4u
M1004 a_36_40# wl bl gnd nfet w=0.8u l=0.4u
+ ad=0p pd=0u as=0.8p ps=3.6u
M1005 vdd wl br gnd nfet w=0.8u l=0.4u
+ ad=0p pd=0u as=0.8p ps=3.6u
C0 vdd 0 2.60fF
technology/scn4m_subm/sp_lib/cell_1w_1r.sp
Vendored
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.SUBCKT cell_1w_1r bl0 br0 bl1 br1 wl0 wl1 vdd gnd
MM9 RA_to_R_right wl1 br1 gnd n w=1.2u l=0.4u
MM8 RA_to_R_right Q gnd gnd n w=1.2u l=0.4u
MM7 RA_to_R_left Q_bar gnd gnd n w=1.2u l=0.4u
MM6 RA_to_R_left wl1 bl1 gnd n w=1.2u l=0.4u
MM5 Q wl0 bl0 gnd n w=0.8u l=0.4u
MM4 Q_bar wl0 br0 gnd n w=0.8u l=0.4u
MM1 Q Q_bar gnd gnd n w=1.6u l=0.4u
MM0 Q_bar Q gnd gnd n w=1.6u l=0.4u
MM3 Q Q_bar vdd vdd p w=0.6u l=0.4u
MM2 Q_bar Q vdd vdd p w=0.6u l=0.4u
.ENDS
technology/scn4m_subm/sp_lib/cell_6t.st0
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****** HSPICE -- M-2017.03 linux64 (Feb 20 2017) ******
Input File: cell_6t.sp
lic:
lic: FLEXlm: SDK_11.6.4
lic: USER: mrg HOSTNAME: 72fb17cef281
lic: HOSTID: 0242ac110002 PID: 69
lic: Using FLEXlm license file:
lic: [email protected]
lic: Checkout 1 hspice
lic: License/Maintenance for hspice will expire on 18-dec-2020/2018.09
lic: 1(in_use)/50(total) FLOATING license(s) on SERVER [email protected]
lic:
init: begin read circuit files, cpu clock= 9.60E-01
option search = /bsoe/software/synopsys/M-2017.03/hspice/parts/a
d
option search = /bsoe/software/synopsys/M-2017.03/hspice/parts/b
ehave
option search = /bsoe/software/synopsys/M-2017.03/hspice/parts/c
omlinear
option search = /bsoe/software/synopsys/M-2017.03/hspice/parts/d
io
option search = /bsoe/software/synopsys/M-2017.03/hspice/parts/f
et
option search = /bsoe/software/synopsys/M-2017.03/hspice/parts/l
in_tech
option search = /bsoe/software/synopsys/M-2017.03/hspice/parts/p
ci
option search = /bsoe/software/synopsys/M-2017.03/hspice/parts/s
ignet
option search = /bsoe/software/synopsys/M-2017.03/hspice/parts/t
i
option search = /bsoe/software/synopsys/M-2017.03/hspice/parts/x
ilinx
option runlvl
init: end read circuit files, cpu clock= 9.60E-01 peak memory= 290 mb
init: begin check errors, cpu clock= 9.60E-01
>error ***** hspice job aborted
lic: Release hspice token(s)
technology/scn4m_subm/sp_lib/replica_cell_1w_1r.sp
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.SUBCKT replica_cell_1w_1r bl0 br0 bl1 br1 wl0 wl1 vdd gnd
MM9 RA_to_R_right wl1 br1 gnd n w=1.2u l=0.4u
MM8 RA_to_R_right Q gnd gnd n w=1.2u l=0.4u
MM7 RA_to_R_left vdd gnd gnd n w=1.2u l=0.4u
MM6 RA_to_R_left wl1 bl1 gnd n w=1.2u l=0.4u
MM5 Q wl0 bl0 gnd n w=0.8u l=0.4u
MM4 vdd wl0 br0 gnd n w=0.8u l=0.4u
MM1 Q vdd gnd gnd n w=1.6u l=0.4u
MM0 vdd Q gnd gnd n w=1.6u l=0.4u
MM3 Q vdd vdd vdd p w=0.6u l=0.4u
MM2 vdd Q vdd vdd p w=0.6u l=0.4u
.ENDS