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Merge branch 'dev' into multiport_characterization

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This commit is contained in:
Hunter Nichols
2019-02-26 22:48:39 -08:00
parent ea51cfdbb4 fa89e11f95
commit 816669b9ca
112 changed files with 794 additions and 24251 deletions
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compiler/tests/04_pbitcell_test.py
+1 -1
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@@ -26,7 +26,7 @@ class pbitcell_test(openram_test):
debug.info(2, "Bitcell with 1 of each port: read/write, write, and read")
tx = pbitcell(name="pbc")
self.local_check(tx)
OPTS.num_rw_ports=0
OPTS.num_w_ports=1
OPTS.num_r_ports=1
compiler/tests/20_sram_1bank_2mux_1w_1r_test.py
Executable
+51
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@@ -0,0 +1,51 @@
#!/usr/bin/env python3
"""
Run a regression test on a 1 bank SRAM
"""
import unittest
from testutils import header,openram_test
import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
import debug
#@unittest.skip("SKIPPING 20_psram_1bank_2mux_1w_1r_test, odd supply routing error")
class psram_1bank_2mux_1w_1r_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
from sram import sram
from sram_config import sram_config
OPTS.bitcell = "bitcell_1w_1r"
OPTS.replica_bitcell="replica_bitcell_1w_1r"
OPTS.num_rw_ports = 0
OPTS.num_w_ports = 1
OPTS.num_r_ports = 1
c = sram_config(word_size=4,
num_words=32,
num_banks=1)
c.num_words=32
c.words_per_row=2
c.recompute_sizes()
debug.info(1, "Layout test for {}rw,{}r,{}w psram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
OPTS.num_r_ports,
OPTS.num_w_ports,
c.word_size,
c.num_words,
c.words_per_row,
c.num_banks))
a = sram(c, "sram")
self.local_check(a, final_verification=True)
globals.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main()
compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib
+3 -3
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@@ -93,7 +93,7 @@ cell (sram_2_16_1_freepdk45){
address : ADDR0;
clocked_on : clk0;
}
pin(DIN0){
pin(DIN0[1:0]){
timing(){
timing_type : setup_rising;
related_pin : "clk0";
@@ -132,7 +132,7 @@ cell (sram_2_16_1_freepdk45){
memory_read(){
address : ADDR0;
}
pin(DOUT0){
pin(DOUT0[1:0]){
timing(){
timing_sense : non_unate;
related_pin : "clk0";
@@ -166,7 +166,7 @@ cell (sram_2_16_1_freepdk45){
direction : input;
capacitance : 0.2091;
max_transition : 0.04;
pin(ADDR0){
pin(ADDR0[3:0]){
timing(){
timing_type : setup_rising;
related_pin : "clk0";
compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib
+3 -3
View File
@@ -93,7 +93,7 @@ cell (sram_2_16_1_freepdk45){
address : ADDR0;
clocked_on : clk0;
}
pin(DIN0){
pin(DIN0[1:0]){
timing(){
timing_type : setup_rising;
related_pin : "clk0";
@@ -132,7 +132,7 @@ cell (sram_2_16_1_freepdk45){
memory_read(){
address : ADDR0;
}
pin(DOUT0){
pin(DOUT0[1:0]){
timing(){
timing_sense : non_unate;
related_pin : "clk0";
@@ -166,7 +166,7 @@ cell (sram_2_16_1_freepdk45){
direction : input;
capacitance : 0.2091;
max_transition : 0.04;
pin(ADDR0){
pin(ADDR0[3:0]){
timing(){
timing_type : setup_rising;
related_pin : "clk0";
compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib
+3 -3
View File
@@ -93,7 +93,7 @@ cell (sram_2_16_1_freepdk45){
address : ADDR0;
clocked_on : clk0;
}
pin(DIN0){
pin(DIN0[1:0]){
timing(){
timing_type : setup_rising;
related_pin : "clk0";
@@ -132,7 +132,7 @@ cell (sram_2_16_1_freepdk45){
memory_read(){
address : ADDR0;
}
pin(DOUT0){
pin(DOUT0[1:0]){
timing(){
timing_sense : non_unate;
related_pin : "clk0";
@@ -166,7 +166,7 @@ cell (sram_2_16_1_freepdk45){
direction : input;
capacitance : 0.2091;
max_transition : 0.04;
pin(ADDR0){
pin(ADDR0[3:0]){
timing(){
timing_type : setup_rising;
related_pin : "clk0";
compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib
+3 -3
View File
@@ -93,7 +93,7 @@ cell (sram_2_16_1_scn4m_subm){
address : ADDR0;
clocked_on : clk0;
}
pin(DIN0){
pin(DIN0[1:0]){
timing(){
timing_type : setup_rising;
related_pin : "clk0";
@@ -132,7 +132,7 @@ cell (sram_2_16_1_scn4m_subm){
memory_read(){
address : ADDR0;
}
pin(DOUT0){
pin(DOUT0[1:0]){
timing(){
timing_sense : non_unate;
related_pin : "clk0";
@@ -166,7 +166,7 @@ cell (sram_2_16_1_scn4m_subm){
direction : input;
capacitance : 9.8242;
max_transition : 0.4;
pin(ADDR0){
pin(ADDR0[3:0]){
timing(){
timing_type : setup_rising;
related_pin : "clk0";
compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib
+3 -3
View File
@@ -93,7 +93,7 @@ cell (sram_2_16_1_scn4m_subm){
address : ADDR0;
clocked_on : clk0;
}
pin(DIN0){
pin(DIN0[1:0]){
timing(){
timing_type : setup_rising;
related_pin : "clk0";
@@ -132,7 +132,7 @@ cell (sram_2_16_1_scn4m_subm){
memory_read(){
address : ADDR0;
}
pin(DOUT0){
pin(DOUT0[1:0]){
timing(){
timing_sense : non_unate;
related_pin : "clk0";
@@ -166,7 +166,7 @@ cell (sram_2_16_1_scn4m_subm){
direction : input;
capacitance : 9.8242;
max_transition : 0.4;
pin(ADDR0){
pin(ADDR0[3:0]){
timing(){
timing_type : setup_rising;
related_pin : "clk0";
compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib
+3 -3
View File
@@ -93,7 +93,7 @@ cell (sram_2_16_1_scn4m_subm){
address : ADDR0;
clocked_on : clk0;
}
pin(DIN0){
pin(DIN0[1:0]){
timing(){
timing_type : setup_rising;
related_pin : "clk0";
@@ -132,7 +132,7 @@ cell (sram_2_16_1_scn4m_subm){
memory_read(){
address : ADDR0;
}
pin(DOUT0){
pin(DOUT0[1:0]){
timing(){
timing_sense : non_unate;
related_pin : "clk0";
@@ -166,7 +166,7 @@ cell (sram_2_16_1_scn4m_subm){
direction : input;
capacitance : 9.8242;
max_transition : 0.4;
pin(ADDR0){
pin(ADDR0[3:0]){
timing(){
timing_type : setup_rising;
related_pin : "clk0";
compiler/tests/testutils.py
+6 -5
View File
@@ -13,7 +13,7 @@ class openram_test(unittest.TestCase):
self.reset()
tempgds = OPTS.openram_temp + "temp.gds"
tempgds = "{0}{1}.gds".format(OPTS.openram_temp,w.name)
w.gds_write(tempgds)
import verify
@@ -28,8 +28,8 @@ class openram_test(unittest.TestCase):
self.reset()
tempspice = OPTS.openram_temp + "temp.sp"
tempgds = OPTS.openram_temp + "temp.gds"
tempspice = "{0}{1}.sp".format(OPTS.openram_temp,a.name)
tempgds = "{0}{1}.gds".format(OPTS.openram_temp,a.name)
a.sp_write(tempspice)
# cannot write gds in netlist_only mode
@@ -37,7 +37,7 @@ class openram_test(unittest.TestCase):
a.gds_write(tempgds)
import verify
result=verify.run_drc(a.name, tempgds)
result=verify.run_drc(a.name, tempgds, extract=True, final_verification=final_verification)
if result != 0:
#zip_file = "/tmp/{0}_{1}".format(a.name,os.getpid())
#debug.info(0,"Archiving failed files to {}.zip".format(zip_file))
@@ -45,7 +45,7 @@ class openram_test(unittest.TestCase):
self.fail("DRC failed: {}".format(a.name))
result=verify.run_lvs(a.name, tempgds, tempspice, final_verification)
result=verify.run_lvs(a.name, tempgds, tempspice, final_verification=final_verification)
if result != 0:
#zip_file = "/tmp/{0}_{1}".format(a.name,os.getpid())
#debug.info(0,"Archiving failed files to {}.zip".format(zip_file))
@@ -54,6 +54,7 @@ class openram_test(unittest.TestCase):
if OPTS.purge_temp:
self.cleanup()
def find_feasible_test_period(self, delay_obj, sram, load, slew):
"""Creates a delay simulation to determine a feasible period for the functional tests to run.