mirror of https://github.com/VLSIDA/OpenRAM.git
126 lines
5.2 KiB
Python
126 lines
5.2 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
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# All rights reserved.
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#
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from openram.sram_factory import factory
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from openram import OPTS
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from .bitcell_base_array import bitcell_base_array
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from openram.base import geometry
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from .pattern import pattern
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class dummy_array(bitcell_base_array):
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"""
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Generate a dummy row/column for the replica array.
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"""
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def __init__(self, rows, cols, column_offset=0, mirror=0, location="", name=""):
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super().__init__(rows=rows, cols=cols, column_offset=column_offset, name=name)
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self.mirror = mirror
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def create_netlist(self):
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""" Create and connect the netlist """
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# This will create a default set of bitline/wordline names
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self.create_all_bitline_names()
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self.create_all_wordline_names()
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self.add_modules()
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self.add_pins()
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self.create_instances()
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def create_layout(self):
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self.place_array()
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self.add_layout_pins()
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self.route_supplies()
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self.add_boundary()
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self.DRC_LVS()
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def add_modules(self):
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""" Add the modules used in this design """
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self.dummy_cell = factory.create(module_type=OPTS.dummy_bitcell)
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self.cell = factory.create(module_type=OPTS.bitcell)
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def create_instances(self):
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""" Create the module instances used in this design """
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self.cell_inst={}
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core_block = [[0 for x in range(2)] for y in range(2)]
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if not self.mirror:
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core_block[0][0] = geometry.instance("core_0_0", mod=self.dummy_cell, is_bitcell=True)
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core_block[0][1] = geometry.instance("core_1_0", mod=self.dummy_cell, is_bitcell=True, mirror='MX')
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core_block[1][0] = geometry.instance("core_0_1", mod=self.dummy_cell, is_bitcell=True, mirror='MY')
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core_block[1][1] = geometry.instance("core_1_1", mod=self.dummy_cell, is_bitcell=True, mirror='XY')
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else:
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core_block[0][0] = geometry.instance("core_0_0", mod=self.dummy_cell, is_bitcell=True, mirror='MY')
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core_block[0][1] = geometry.instance("core_1_0", mod=self.dummy_cell, is_bitcell=True, mirror='XY')
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core_block[1][0] = geometry.instance("core_0_1", mod=self.dummy_cell, is_bitcell=True)
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core_block[1][1] = geometry.instance("core_1_1", mod=self.dummy_cell, is_bitcell=True, mirror='MX')
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self.pattern = pattern(self, "dummy_array", core_block, num_rows=self.row_size, num_cols=self.column_size)
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self.pattern.connect_array()
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def add_pins(self):
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# bitline pins are not added because they are floating
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for bl_name in self.get_bitline_names():
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self.add_pin(bl_name, "INOUT")
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# bitline pins are not added because they are floating
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for wl_name in self.get_wordline_names():
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self.add_pin(wl_name, "INPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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def add_layout_pins(self):
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""" Add the layout pins """
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# Add the bitline metal, but not as pins since they are going to just be floating
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# For some reason, LVS has an issue if we don't add this metal
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bitline_names = self.cell.get_all_bitline_names()
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for col in range(self.column_size):
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for port in self.all_ports:
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bl_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port])
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self.add_layout_pin(text="bl_{0}_{1}".format(port, col),
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layer=bl_pin.layer,
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offset=bl_pin.ll().scale(1, 0),
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width=bl_pin.width(),
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height=self.height)
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br_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port + 1])
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self.add_layout_pin(text="br_{0}_{1}".format(port, col),
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layer=br_pin.layer,
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offset=br_pin.ll().scale(1, 0),
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width=br_pin.width(),
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height=self.height)
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wl_names = self.cell.get_all_wl_names()
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for row in range(self.row_size):
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for port in self.all_ports:
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wl_pins = self.cell_inst[row, 0].get_pins(wl_names[port])
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for wl_pin in wl_pins:
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self.add_layout_pin(text="wl_{0}_{1}".format(port, row),
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layer=wl_pin.layer,
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offset=wl_pin.ll().scale(0, 1),
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width=self.width,
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height=wl_pin.height())
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def route_supplies(self):
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# Copy a vdd/gnd layout pin from every cell
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for row in range(self.row_size):
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for col in range(self.column_size):
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inst = self.cell_inst[row, col]
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for pin_name in ["vdd", "gnd"]:
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self.copy_layout_pin(inst, pin_name)
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def input_load(self):
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# FIXME: This appears to be old code from previous characterization. Needs to be updated.
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wl_wire = self.gen_wl_wire()
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return wl_wire.return_input_cap()
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