Added corner information for analytical power estimation.

compiler/modules/bitcell_array.py

@@ -147,19 +147,19 @@ class bitcell_array(design.design):
         return self.return_delay(cell_delay.delay+wl_to_cell_delay.delay,
                                  wl_to_cell_delay.slew)
                         
-    def analytical_power(self, proc, vdd, temp, load):
+    def analytical_power(self, corner, load):
         """Power of Bitcell array and bitline in nW."""
-        from tech import drc
+        from tech import drc, parameter
         
         # Dynamic Power from Bitline
         bl_wire = self.gen_bl_wire()
         cell_load = 2 * bl_wire.return_input_cap() 
-        bl_swing = 0.1 #This should probably be defined in the tech file or input
+        bl_swing = parameter["rbl_height_percentage"]
         freq = spice["default_event_rate"]
-        bitline_dynamic = bl_swing*cell_load*vdd*vdd*freq #not sure if calculation is correct
+        bitline_dynamic = self.calc_dynamic_power(corner, cell_load, freq, swing=bl_swing)
         
         #Calculate the bitcell power which currently only includes leakage 
-        cell_power = self.cell.analytical_power(proc, vdd, temp, load)
+        cell_power = self.cell.analytical_power(corner, load)
         
         #Leakage power grows with entire array and bitlines.
         total_power = self.return_power(cell_power.dynamic + bitline_dynamic * self.column_size,

compiler/modules/dff.py

@@ -21,11 +21,11 @@ class dff(design.design):
         self.height = dff.height
         self.pin_map = dff.pin_map
     
-    def analytical_power(self, proc, vdd, temp, load):
+    def analytical_power(self, corner, load):
         """Returns dynamic and leakage power. Results in nW"""
         c_eff = self.calculate_effective_capacitance(load)
-        f = spice["default_event_rate"]
-        power_dyn = c_eff*vdd*vdd*f
+        freq = spice["default_event_rate"]
+        power_dyn = self.calc_dynamic_power(corner, c_eff, freq)
         power_leak = spice["msflop_leakage"]
         
         total_power = self.return_power(power_dyn, power_leak)

compiler/modules/sense_amp.py

@@ -38,7 +38,7 @@ class sense_amp(design.design):
         result = self.cal_delay_with_rc(corner, r = r, c =  c_para+load, slew = slew)
         return self.return_delay(result.delay, result.slew)
 
-    def analytical_power(self, proc, vdd, temp, load):
+    def analytical_power(self, corner, load):
         """Returns dynamic and leakage power. Results in nW"""
         #Power in this module currently not defined. Returns 0 nW (leakage and dynamic).
         total_power = self.return_power()

compiler/modules/single_level_column_mux_array.py

@@ -218,11 +218,11 @@ class single_level_column_mux_array(design.design):
 
     def analytical_delay(self, corner, vdd, slew, load=0.0):
         from tech import spice, parameter
-        proc,volt,temp = corner
+        proc,vdd,temp = corner
         r = spice["min_tx_r"]/(self.mux.ptx_width/parameter["min_tx_size"])
         #Drains of mux transistors make up capacitance. 
         c_para = spice["min_tx_drain_c"]*(self.mux.ptx_width/parameter["min_tx_size"])*self.words_per_row#ff
-        volt_swing = spice["v_threshold_typical"]/volt
+        volt_swing = spice["v_threshold_typical"]/vdd
         
         result = self.cal_delay_with_rc(corner, r = r, c =  c_para+load, slew = slew, swing = volt_swing)
         return self.return_delay(result.delay, result.slew)            

compiler/modules/tri_gate.py

@@ -33,7 +33,7 @@ class tri_gate(design.design):
         c_para = spice["min_tx_drain_c"]
         return self.cal_delay_with_rc(corner, r = r, c =  c_para+load, slew = slew)
         
-    def analytical_power(self, proc, vdd, temp, load):
+    def analytical_power(self, corner, load):
         """Returns dynamic and leakage power. Results in nW"""
         #Power in this module currently not defined. Returns 0 nW (leakage and dynamic).
         total_power = self.return_power()