Added corner information for analytical power estimation.

compiler/bitcells/bitcell.py

@@ -66,7 +66,7 @@ class bitcell(design.design):
         column_pins = ["br"]
         return column_pins
         
-    def analytical_power(self, proc, vdd, temp, load):
+    def analytical_power(self, corner, load):
         """Bitcell power in nW. Only characterizes leakage."""
         from tech import spice
         leakage = spice["bitcell_leakage"]

compiler/bitcells/bitcell_1rw_1r.py

@@ -89,7 +89,7 @@ class bitcell_1rw_1r(design.design):
         column_pins = ["br0"]
         return column_pins
     
-    def analytical_power(self, proc, vdd, temp, load):
+    def analytical_power(self, corner, load):
         """Bitcell power in nW. Only characterizes leakage."""
         from tech import spice
         leakage = spice["bitcell_leakage"]

compiler/bitcells/bitcell_1w_1r.py

@@ -89,7 +89,7 @@ class bitcell_1w_1r(design.design):
         column_pins = ["br0"]
         return column_pins
     
-    def analytical_power(self, proc, vdd, temp, load):
+    def analytical_power(self, corner, load):
         """Bitcell power in nW. Only characterizes leakage."""
         from tech import spice
         leakage = spice["bitcell_leakage"]

compiler/bitcells/pbitcell.py

@@ -874,7 +874,7 @@ class pbitcell(design.design):
         result = self.cal_delay_with_rc(corner, r = r, c =  c_para+load, slew = slew, swing = swing)
         return result
         
-    def analytical_power(self, proc, vdd, temp, load):
+    def analytical_power(self, corner, load):
         """Bitcell power in nW. Only characterizes leakage."""
         from tech import spice
         leakage = spice["bitcell_leakage"]