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Add bitlines to dummy modules

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mrg
2020-10-16 13:43:56 -07:00
parent 20be7caf98
commit 804814d18d
2 changed files with 4 additions and 1 deletions
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compiler/modules/replica_bitcell_array.py
+1 -1
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@@ -304,7 +304,7 @@ class replica_bitcell_array(bitcell_base_array):
for port in self.all_ports:
self.dummy_row_replica_insts.append(self.add_inst(name="dummy_row_{}".format(port),
mod=self.dummy_row))
self.connect_inst([x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[port]] + self.supplies)
self.connect_inst(self.all_bitline_names + [x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[port]] + self.supplies)
# Top/bottom dummy rows or col caps
self.dummy_row_insts = []