diff --git a/compiler/modules/dummy_array.py b/compiler/modules/dummy_array.py
index 9fde2a67..465fb9d8 100644
--- a/compiler/modules/dummy_array.py
+++ b/compiler/modules/dummy_array.py
@@ -60,6 +60,9 @@ class dummy_array(bitcell_base_array):
 
     def add_pins(self):
         # bitline pins are not added because they are floating
+        for bl_name in self.get_bitline_names():
+            self.add_pin(bl_name, "INOUT")
+        # bitline pins are not added because they are floating
         for wl_name in self.get_wordline_names():
             self.add_pin(wl_name, "INPUT")
         self.add_pin("vdd", "POWER")
diff --git a/compiler/modules/replica_bitcell_array.py b/compiler/modules/replica_bitcell_array.py
index 0444a2cc..12c1706e 100644
--- a/compiler/modules/replica_bitcell_array.py
+++ b/compiler/modules/replica_bitcell_array.py
@@ -304,7 +304,7 @@ class replica_bitcell_array(bitcell_base_array):
         for port in self.all_ports:
             self.dummy_row_replica_insts.append(self.add_inst(name="dummy_row_{}".format(port),
                                                                 mod=self.dummy_row))
-            self.connect_inst([x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[port]] + self.supplies)
+            self.connect_inst(self.all_bitline_names + [x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[port]] + self.supplies)
 
         # Top/bottom dummy rows or col caps
         self.dummy_row_insts = []