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Add bitlines to dummy modules

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mrg
2020-10-16 13:43:56 -07:00
parent 20be7caf98
commit 804814d18d
2 changed files with 4 additions and 1 deletions
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compiler/modules/dummy_array.py
+3
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@@ -60,6 +60,9 @@ class dummy_array(bitcell_base_array):
def add_pins(self):
# bitline pins are not added because they are floating
for bl_name in self.get_bitline_names():
self.add_pin(bl_name, "INOUT")
# bitline pins are not added because they are floating
for wl_name in self.get_wordline_names():
self.add_pin(wl_name, "INPUT")
self.add_pin("vdd", "POWER")