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Fix pbitcell erros
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@@ -70,7 +70,7 @@ class dff_array(design.design):
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mod=self.dff)
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instance_ports = [self.get_din_name(row, col),
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self.get_dout_name(row, col)]
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for port in self.dff.pin_names:
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for port in self.dff.pins:
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if port != 'D' and port != 'Q':
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instance_ports.append(port)
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self.connect_inst(instance_ports)
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