luke/OpenRAM
1
0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-09-07 03:20:39 +02:00
Code Issues Packages Projects Releases Wiki Activity

Fix pbitcell erros

Browse Source
This commit is contained in:
mrg
2020-11-13 15:55:55 -08:00
parent c472a94f1e
commit 8021430122
32 changed files with 236 additions and 500 deletions
Download Patch File Download Diff File Expand all files Collapse all files
compiler/modules/bitcell_base_array.py
+2 -3
View File
@@ -7,7 +7,6 @@
#
import debug
import design
from tech import cell_properties
from sram_factory import factory
from globals import OPTS
@@ -174,7 +173,7 @@ class bitcell_base_array(design.design):
tempx = xoffset
dir_y = False
# If we mirror the current cell on the y axis adjust the x position
if cell_properties.bitcell.mirror.y and (col + col_offset) % 2:
if self.cell.mirror.y and (col + col_offset) % 2:
tempx = xoffset + self.cell.width
dir_y = True
return (tempx, dir_y)
@@ -183,7 +182,7 @@ class bitcell_base_array(design.design):
tempy = yoffset
dir_x = False
# If we mirror the current cell on the x axis adjust the y position
if cell_properties.bitcell.mirror.x and (row + row_offset) % 2:
if self.cell.mirror.x and (row + row_offset) % 2:
tempy = yoffset + self.cell.height
dir_x = True
return (tempy, dir_x)
compiler/modules/col_cap_array.py
+2 -7
View File
@@ -26,12 +26,9 @@ class col_cap_array(bitcell_base_array):
def create_netlist(self):
""" Create and connect the netlist """
# This will create a default set of bitline/wordline names
try:
end_caps_enabled = cell_properties.bitcell.end_caps
except AttributeError:
end_caps_enabled = False
self.cell = factory.create(module_type=OPTS.bitcell)
if not end_caps_enabled:
if not self.cell.end_caps:
self.create_all_wordline_names()
self.create_all_bitline_names()
@@ -51,8 +48,6 @@ class col_cap_array(bitcell_base_array):
self.dummy_cell = factory.create(module_type="col_cap_{}".format(OPTS.bitcell))
self.add_mod(self.dummy_cell)
self.cell = factory.create(module_type=OPTS.bitcell)
def create_instances(self):
""" Create the module instances used in this design """
self.cell_inst = {}
compiler/modules/control_logic.py
-3
View File
@@ -662,9 +662,6 @@ class control_logic(design.design):
self.ctrl_dff_inst=self.add_inst(name="ctrl_dffs",
mod=self.ctrl_dff_array)
inst_pins = self.input_list + self.dff_output_list + ["clk_buf"] + self.supply_list
if props.dff_buff_array.add_body_contacts:
inst_pins.append("vpb")
inst_pins.append("vnb")
self.connect_inst(inst_pins)
def place_dffs(self):
compiler/modules/dff_array.py
+1 -1
View File
@@ -70,7 +70,7 @@ class dff_array(design.design):
mod=self.dff)
instance_ports = [self.get_din_name(row, col),
self.get_dout_name(row, col)]
for port in self.dff.pin_names:
for port in self.dff.pins:
if port != 'D' and port != 'Q':
instance_ports.append(port)
self.connect_inst(instance_ports)
compiler/modules/dff_buf.py
+15 -23
View File
@@ -72,30 +72,22 @@ class dff_buf(design.design):
self.add_mod(self.inv2)
def add_pins(self):
self.add_pin("D", "INPUT")
self.add_pin("Q", "OUTPUT")
self.add_pin("Qb", "OUTPUT")
self.add_pin("clk", "INPUT")
self.add_pin("vdd", "POWER")
self.add_pin("gnd", "GROUND")
if props.dff_buff.add_body_contacts:
self.add_pin("vpb", "INPUT")
self.add_pin("vpn", "INPUT")
self.add_pin_list(props.dff_buf.port_names,
props.dff_buf.port_types)
def create_instances(self):
self.dff_inst=self.add_inst(name="dff_buf_dff",
mod=self.dff)
self.connect_inst(["D", "qint", "clk", "vdd", "gnd"])
self.connect_inst([props.dff_buf.pin.D, "qint", props.dff_buf.pin.clk, props.dff_buf.pin.vdd, props.dff_buf.pin.gnd])
self.inv1_inst=self.add_inst(name="dff_buf_inv1",
mod=self.inv1)
self.connect_inst(["qint", "Qb", "vdd", "gnd"])
self.connect_inst(["qint", "Qb", props.dff_buf.pin.vdd, props.dff_buf.pin.gnd])
self.inv2_inst=self.add_inst(name="dff_buf_inv2",
mod=self.inv2)
self.connect_inst(["Qb", "Q", "vdd", "gnd"])
self.connect_inst(["Qb", props.dff_buf.pin.Q, props.dff_buf.pin.vdd, props.dff_buf.pin.gnd])
def place_instances(self):
# Add the DFF
@@ -129,7 +121,7 @@ class dff_buf(design.design):
self.route_layer = "m1"
# Route dff q to inv1 a
q_pin = self.dff_inst.get_pin("Q")
q_pin = self.dff_inst.get_pin(props.dff.pin.Q)
a1_pin = self.inv1_inst.get_pin("A")
mid1 = vector(a1_pin.cx(), q_pin.cy())
self.add_path(q_pin.layer, [q_pin.center(), mid1, a1_pin.center()], width=q_pin.height())
@@ -146,30 +138,30 @@ class dff_buf(design.design):
def add_layout_pins(self):
# Continous vdd rail along with label.
vdd_pin=self.dff_inst.get_pin("vdd")
self.add_layout_pin(text="vdd",
vdd_pin=self.dff_inst.get_pin(props.dff.pin.vdd)
self.add_layout_pin(text=props.dff_buf.pin.vdd,
layer=vdd_pin.layer,
offset=vdd_pin.ll(),
width=self.width,
height=vdd_pin.height())
# Continous gnd rail along with label.
gnd_pin=self.dff_inst.get_pin("gnd")
self.add_layout_pin(text="gnd",
gnd_pin=self.dff_inst.get_pin(props.dff.pin.gnd)
self.add_layout_pin(text=props.dff_buf.pin.gnd,
layer=gnd_pin.layer,
offset=gnd_pin.ll(),
width=self.width,
height=vdd_pin.height())
clk_pin = self.dff_inst.get_pin("clk")
self.add_layout_pin(text="clk",
clk_pin = self.dff_inst.get_pin(props.dff.pin.clk)
self.add_layout_pin(text=props.dff_buf.pin.clk,
layer=clk_pin.layer,
offset=clk_pin.ll(),
width=clk_pin.width(),
height=clk_pin.height())
din_pin = self.dff_inst.get_pin("D")
self.add_layout_pin(text="D",
din_pin = self.dff_inst.get_pin(props.dff_buf.pin.D)
self.add_layout_pin(text=props.dff_buf.pin.D,
layer=din_pin.layer,
offset=din_pin.ll(),
width=din_pin.width(),
@@ -178,7 +170,7 @@ class dff_buf(design.design):
dout_pin = self.inv2_inst.get_pin("Z")
mid_pos = dout_pin.center() + vector(self.m2_nonpref_pitch, 0)
q_pos = mid_pos - vector(0, 2 * self.m2_nonpref_pitch)
self.add_layout_pin_rect_center(text="Q",
self.add_layout_pin_rect_center(text=props.dff_buf.pin.Q,
layer="m2",
offset=q_pos)
self.add_path(self.route_layer, [dout_pin.center(), mid_pos, q_pos])
compiler/modules/dff_buf_array.py
+1 -8
View File
@@ -65,10 +65,6 @@ class dff_buf_array(design.design):
self.add_pin("vdd", "POWER")
self.add_pin("gnd", "GROUND")
if props.dff_buff_array.add_body_contacts:
self.add_pin("vpb", "INPUT")
self.add_pin("vnb", "INPUT")
def add_modules(self):
self.dff = factory.create(module_type="dff_buf",
inv1_size=self.inv1_size,
@@ -88,9 +84,6 @@ class dff_buf_array(design.design):
"clk",
"vdd",
"gnd"]
if props.dff_buff_array.add_body_contacts:
inst_ports.append("vpb")
inst_ports.append("vnb")
self.connect_inst(inst_ports)
def place_dff_array(self):
@@ -155,7 +148,7 @@ class dff_buf_array(design.design):
def route_supplies(self):
for row in range(self.rows):
vdd0_pin=self.dff_insts[row, 0].get_pin("vdd")
vdd0_pin=self.dff_insts[row, 0].get_pin(props.dff.pin.vdd)
vddn_pin=self.dff_insts[row, self.columns - 1].get_pin("vdd")
self.add_path(vdd0_pin.layer, [vdd0_pin.lc(), vddn_pin.rc()], width=vdd0_pin.height())
compiler/modules/precharge_array.py
+3 -2
View File
@@ -10,7 +10,6 @@ import debug
from vector import vector
from sram_factory import factory
from globals import OPTS
from tech import cell_properties
class precharge_array(design.design):
@@ -79,6 +78,8 @@ class precharge_array(design.design):
bitcell_br=self.bitcell_br)
self.add_mod(self.pc_cell)
self.cell = factory.create(module_type=OPTS.bitcell)
def add_layout_pins(self):
en_pin = self.pc_cell.get_pin("en_bar")
@@ -120,7 +121,7 @@ class precharge_array(design.design):
self.offsets = [n * self.pc_cell.width for n in range(self.columns)]
for i, xoffset in enumerate(self.offsets):
if cell_properties.bitcell.mirror.y and (i + self.column_offset) % 2:
if self.cell.mirror.y and (i + self.column_offset) % 2:
mirror = "MY"
tempx = xoffset + self.pc_cell.width
else:
compiler/modules/replica_bitcell_array.py
+9 -31
View File
@@ -63,13 +63,8 @@ class replica_bitcell_array(bitcell_base_array):
# Two dummy cols plus replica if we add the column
self.extra_cols = len(self.left_rbl) + len(self.right_rbl)
try:
end_caps_enabled = cell_properties.bitcell.end_caps
except AttributeError:
end_caps_enabled = False
# If we aren't using row/col caps, then we need to use the bitcell
if not end_caps_enabled:
if not self.cell.end_caps:
self.extra_rows += 2
self.extra_cols += 2
@@ -144,10 +139,6 @@ class replica_bitcell_array(bitcell_base_array):
column_offset=column_offset,
replica_bit=replica_bit)
self.add_mod(self.replica_columns[port])
try:
end_caps_enabled = cell_properties.bitcell.end_caps
except AttributeError:
end_caps_enabled = False
# Dummy row
self.dummy_row = factory.create(module_type="dummy_array",
@@ -159,7 +150,7 @@ class replica_bitcell_array(bitcell_base_array):
self.add_mod(self.dummy_row)
# Dummy Row or Col Cap, depending on bitcell array properties
col_cap_module_type = ("col_cap_array" if end_caps_enabled else "dummy_array")
col_cap_module_type = ("col_cap_array" if self.cell.end_caps else "dummy_array")
self.col_cap_top = factory.create(module_type=col_cap_module_type,
cols=self.column_size,
rows=1,
@@ -179,7 +170,7 @@ class replica_bitcell_array(bitcell_base_array):
self.add_mod(self.col_cap_bottom)
# Dummy Col or Row Cap, depending on bitcell array properties
row_cap_module_type = ("row_cap_array" if end_caps_enabled else "dummy_array")
row_cap_module_type = ("row_cap_array" if self.cell.end_caps else "dummy_array")
self.row_cap_left = factory.create(module_type=row_cap_module_type,
cols=1,
@@ -240,11 +231,6 @@ class replica_bitcell_array(bitcell_base_array):
self.add_pin_list(self.rbl_bitline_names[port], "INOUT")
def add_wordline_pins(self):
try:
end_caps_enabled = cell_properties.bitcell.end_caps
except AttributeError:
end_caps_enabled = False
# Wordlines to ground
self.gnd_wordline_names = []
@@ -385,14 +371,10 @@ class replica_bitcell_array(bitcell_base_array):
def add_replica_columns(self):
""" Add replica columns on left and right of array """
try:
end_caps_enabled = cell_properties.bitcell.end_caps
except AttributeError:
end_caps_enabled = False
# Grow from left to right, toward the array
for bit, port in enumerate(self.left_rbl):
if not end_caps_enabled:
if not self.cell.end_caps:
offset = self.bitcell_offset.scale(-len(self.left_rbl) + bit, -self.rbl[0] - 1) + self.strap_offset.scale(-len(self.left_rbl) + bit, 0) + self.unused_offset
else:
offset = self.bitcell_offset.scale(-len(self.left_rbl) + bit, -self.rbl[0] - (self.col_end_offset.y/self.cell.height)) + self.strap_offset.scale(-len(self.left_rbl) + bit, 0) + self.unused_offset
@@ -400,7 +382,7 @@ class replica_bitcell_array(bitcell_base_array):
self.replica_col_insts[bit].place(offset)
# Grow to the right of the bitcell array, array outward
for bit, port in enumerate(self.right_rbl):
if not end_caps_enabled:
if not self.cell.end_caps:
offset = self.bitcell_array_inst.lr() + self.bitcell_offset.scale(bit, -self.rbl[0] - 1) + self.strap_offset.scale(bit, -self.rbl[0] - 1)
else:
offset = self.bitcell_array_inst.lr() + self.bitcell_offset.scale(bit, -self.rbl[0] - (self.col_end_offset.y/self.cell.height)) + self.strap_offset.scale(bit, -self.rbl[0] - 1)
@@ -422,15 +404,11 @@ class replica_bitcell_array(bitcell_base_array):
def add_end_caps(self):
""" Add dummy cells or end caps around the array """
try:
end_caps_enabled = cell_properties.bitcell.end_caps
except AttributeError:
end_caps_enabled = False
# FIXME: These depend on the array size itself
# Far top dummy row (first row above array is NOT flipped)
flip_dummy = self.rbl[1] % 2
if not end_caps_enabled:
if not self.cell.end_caps:
dummy_row_offset = self.bitcell_offset.scale(0, self.rbl[1] + flip_dummy) + self.bitcell_array_inst.ul()
else:
dummy_row_offset = self.bitcell_offset.scale(0, self.rbl[1] + flip_dummy) + self.bitcell_array_inst.ul()
@@ -440,7 +418,7 @@ class replica_bitcell_array(bitcell_base_array):
# FIXME: These depend on the array size itself
# Far bottom dummy row (first row below array IS flipped)
flip_dummy = (self.rbl[0] + 1) % 2
if not end_caps_enabled:
if not self.cell.end_caps:
dummy_row_offset = self.bitcell_offset.scale(0, -self.rbl[0] - 1 + flip_dummy) + self.unused_offset
else:
dummy_row_offset = self.bitcell_offset.scale(0, -self.rbl[0] - (self.col_end_offset.y/self.cell.height) + flip_dummy) + self.unused_offset
@@ -448,7 +426,7 @@ class replica_bitcell_array(bitcell_base_array):
mirror="MX" if flip_dummy else "R0")
# Far left dummy col
# Shifted down by the number of left RBLs even if we aren't adding replica column to this bitcell array
if not end_caps_enabled:
if not self.cell.end_caps:
dummy_col_offset = self.bitcell_offset.scale(-len(self.left_rbl) - 1, -self.rbl[0] - 1) + self.unused_offset
else:
dummy_col_offset = self.bitcell_offset.scale(-(len(self.left_rbl)*(1+self.strap_offset.x/self.cell.width)) - (self.row_end_offset.x/self.cell.width), -len(self.left_rbl) - (self.col_end_offset.y/self.cell.height))
@@ -456,7 +434,7 @@ class replica_bitcell_array(bitcell_base_array):
self.dummy_col_insts[0].place(offset=dummy_col_offset)
# Far right dummy col
# Shifted down by the number of left RBLs even if we aren't adding replica column to this bitcell array
if not end_caps_enabled:
if not self.cell.end_caps:
dummy_col_offset = self.bitcell_offset.scale(len(self.right_rbl), -self.rbl[0] - 1) + self.bitcell_array_inst.lr()
else:
dummy_col_offset = self.bitcell_offset.scale(len(self.right_rbl)*(1+self.strap_offset.x/self.cell.width), -self.rbl[0] - (self.col_end_offset.y/self.cell.height)) + self.bitcell_array_inst.lr()
compiler/modules/replica_column.py
+10 -20
View File
@@ -5,7 +5,7 @@
#
import debug
from bitcell_base_array import bitcell_base_array
from tech import cell_properties
from tech import cell_properties as props
from sram_factory import factory
from vector import vector
from globals import OPTS
@@ -30,11 +30,9 @@ class replica_column(bitcell_base_array):
self.replica_bit = replica_bit
# left, right, regular rows plus top/bottom dummy cells
self.total_size = self.left_rbl + rows + self.right_rbl
try:
if not cell_properties.bitcell.end_caps:
self.total_size += 2
except AttributeError:
self.total_size += 2
# For end caps
self.total_size += 2
self.column_offset = column_offset
@@ -82,20 +80,17 @@ class replica_column(bitcell_base_array):
self.dummy_cell = factory.create(module_type=OPTS.dummy_bitcell)
self.add_mod(self.dummy_cell)
try:
edge_module_type = ("col_cap" if cell_properties.bitcell.end_caps else "dummy")
edge_module_type = ("col_cap" if self.cell.end_caps else "dummy")
except AttributeError:
edge_module_type = "dummy"
self.edge_cell = factory.create(module_type=edge_module_type + "_" + OPTS.bitcell)
self.add_mod(self.edge_cell)
# Used for pin names only
self.cell = factory.create(module_type=OPTS.bitcell)
def create_instances(self):
self.cell_inst = {}
try:
end_caps_enabled = cell_properties.bitcell.end_caps
except AttributeError:
end_caps_enabled = False
for row in range(self.total_size):
name="rbc_{0}".format(row)
@@ -113,7 +108,7 @@ class replica_column(bitcell_base_array):
elif (row == 0 or row == self.total_size - 1):
self.cell_inst[row]=self.add_inst(name=name,
mod=self.edge_cell)
if end_caps_enabled:
if self.cell.end_caps:
self.connect_inst(self.get_bitcell_pins_col_cap(row, 0))
else:
self.connect_inst(self.get_bitcell_pins(row, 0))
@@ -131,13 +126,13 @@ class replica_column(bitcell_base_array):
# column that needs to be flipped.
dir_y = False
xoffset = 0
if cell_properties.bitcell.mirror.y and self.column_offset % 2:
if self.replica_cell.mirror.y and self.column_offset % 2:
dir_y = True
xoffset = self.replica_cell.width
for row in range(self.total_size):
# name = "bit_r{0}_{1}".format(row, "rbl")
dir_x = cell_properties.bitcell.mirror.x and (row + rbl_offset) % 2
dir_x = self.replica_cell.mirror.x and (row + rbl_offset) % 2
offset = vector(xoffset, self.cell.height * (row + (row + rbl_offset) % 2))
@@ -169,12 +164,7 @@ class replica_column(bitcell_base_array):
width=bl_pin.width(),
height=self.height)
try:
end_caps_enabled = cell_properties.bitcell.end_caps
except AttributeError:
end_caps_enabled = False
if end_caps_enabled:
if self.cell.end_caps:
row_range_max = self.total_size - 1
row_range_min = 1
else:
compiler/modules/sense_amp_array.py
+2 -4
View File
@@ -10,7 +10,6 @@ from vector import vector
from sram_factory import factory
import debug
from globals import OPTS
from tech import cell_properties
class sense_amp_array(design.design):
@@ -92,7 +91,6 @@ class sense_amp_array(design.design):
def add_modules(self):
self.amp = factory.create(module_type="sense_amp")
self.add_mod(self.amp)
# This is just used for measurements,
@@ -122,7 +120,7 @@ class sense_amp_array(design.design):
self.offsets.append(i * self.bitcell.width)
for i, xoffset in enumerate(self.offsets[0:self.num_cols:self.words_per_row]):
if cell_properties.bitcell.mirror.y and (i * self.words_per_row + self.column_offset) % 2:
if self.bitcell.mirror.y and (i * self.words_per_row + self.column_offset) % 2:
mirror = "MY"
xoffset = xoffset + self.amp_spacing
else:
@@ -134,7 +132,7 @@ class sense_amp_array(design.design):
# place spare sense amps (will share the same enable as regular sense amps)
for i, xoffset in enumerate(self.offsets[self.num_cols:]):
index = self.word_size + i
if cell_properties.bitcell.mirror.y and (index + self.column_offset) % 2:
if self.bitcell.mirror.y and (index + self.column_offset) % 2:
mirror = "MY"
xoffset = xoffset + self.amp_width
else:
compiler/modules/write_driver_array.py
+2 -3
View File
@@ -12,7 +12,6 @@ from tech import drc
from sram_factory import factory
from vector import vector
from globals import OPTS
from tech import cell_properties
class write_driver_array(design.design):
@@ -161,7 +160,7 @@ class write_driver_array(design.design):
self.offsets.append(i * self.driver_spacing)
for i, xoffset in enumerate(self.offsets[0:self.columns:self.words_per_row]):
if cell_properties.bitcell.mirror.y and (i * self.words_per_row + self.column_offset) % 2:
if self.bitcell.mirror.y and (i * self.words_per_row + self.column_offset) % 2:
mirror = "MY"
xoffset = xoffset + self.driver.width
else:
@@ -174,7 +173,7 @@ class write_driver_array(design.design):
for i, xoffset in enumerate(self.offsets[self.columns:]):
index = self.word_size + i
if cell_properties.bitcell.mirror.y and (index + self.column_offset) % 2:
if self.bitcell.mirror.y and (index + self.column_offset) % 2:
mirror = "MY"
xoffset = xoffset + self.driver.width
else: