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fix

This commit is contained in:
Bugra Onal 2022-07-28 17:00:16 -07:00
parent 8f955207d3
commit 7fe0f647ef
1 changed files with 1 additions and 1 deletions
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2
compiler/modules/sram.py
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@ -42,7 +42,7 @@ class sram():
if self.num_banks != 1: if self.num_banks != 1:
from sram_multibank import sram_multibank from sram_multibank import sram_multibank
mb = sram_multibank(s) mb = sram_multibank(self.s)
mb.verilog_write() mb.verilog_write()
self.s.create_netlist() self.s.create_netlist()