Added an exclusion for unused column mux paths to prevent multiple outputs paths in graph.

compiler/modules/bank.py

@@ -1105,3 +1105,8 @@ class bank(design.design):
         """
         self.bitcell_array.clear_exclude_bits()
 
+    def graph_exclude_column_mux(self, column_include_num, port):
+        """
+        Excludes all columns muxes unrelated to the target bit being simulated.
+        """
+        self.port_data[port].graph_exclude_column_mux(column_include_num)

compiler/modules/column_mux_array.py

@@ -230,3 +230,16 @@ class column_mux_array(design.design):
                                       to_layer=self.sel_layer,
                                       offset=br_out_offset_begin,
                                       directions=self.via_directions)
+
+    def graph_exclude_columns(self, column_include_num):
+        """
+        Excludes all columns muxes unrelated to the target bit being simulated.
+        Each mux in mux_inst corresponds to respective column in bitcell array.
+        """
+        #stop = 34
+        for i in range(len(self.mux_inst)):
+            if i != column_include_num:
+                self.graph_inst_exclude.add(self.mux_inst[i])
+                debug.info(0, "Excluded mux {}".format(i))
+            #if i == stop:
+             #   break

compiler/modules/port_data.py

@@ -856,3 +856,10 @@ class port_data(design.design):
         """Precharge adds a loop between bitlines, can be excluded to reduce complexity"""
         if self.precharge_array_inst:
             self.graph_inst_exclude.add(self.precharge_array_inst)
+
+    def graph_exclude_column_mux(self, column_include_num):
+        """
+        Excludes all columns muxes unrelated to the target bit being simulated.
+        """
+        if self.column_mux_array:
+            self.column_mux_array.graph_exclude_columns(column_include_num)