diff --git a/compiler/characterizer/simulation.py b/compiler/characterizer/simulation.py
index 423fe62f..acc3139d 100644
--- a/compiler/characterizer/simulation.py
+++ b/compiler/characterizer/simulation.py
@@ -532,7 +532,11 @@ class simulation():
 
         self.sram.clear_exclude_bits() # Removes previous bit exclusions
         self.sram.graph_exclude_bits(self.wordline_row, self.bitline_column)
-
+        port=0 #FIXME, port_data requires a port specification, assuming single port for now
+        if self.words_per_row > 1:
+            self.sram.graph_exclude_column_mux(self.bitline_column, port)
+        
+        debug.info(0, "self.bitline_column={}".format(self.bitline_column))
         # Generate new graph every analysis as edges might change depending on test bit
         self.graph = graph_util.timing_graph()
         self.sram_instance_name = "X{}".format(self.sram.name)
@@ -554,6 +558,7 @@ class simulation():
         """
         net_found = False
         for path in paths:
+            debug.info(0, "path={}".format(path))
             aliases = self.sram.find_aliases(self.sram_instance_name, self.pins, path, internal_net, mod, exclusion_set)
             if net_found and len(aliases) >= 1:
                 debug.error('Found multiple paths with {} net.'.format(internal_net), 1)
diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py
index 99ad8350..ffff10ff 100644
--- a/compiler/modules/bank.py
+++ b/compiler/modules/bank.py
@@ -1105,3 +1105,8 @@ class bank(design.design):
         """
         self.bitcell_array.clear_exclude_bits()
 
+    def graph_exclude_column_mux(self, column_include_num, port):
+        """
+        Excludes all columns muxes unrelated to the target bit being simulated.
+        """
+        self.port_data[port].graph_exclude_column_mux(column_include_num)
diff --git a/compiler/modules/column_mux_array.py b/compiler/modules/column_mux_array.py
index 4aa23dfe..11502142 100644
--- a/compiler/modules/column_mux_array.py
+++ b/compiler/modules/column_mux_array.py
@@ -230,3 +230,16 @@ class column_mux_array(design.design):
                                       to_layer=self.sel_layer,
                                       offset=br_out_offset_begin,
                                       directions=self.via_directions)
+
+    def graph_exclude_columns(self, column_include_num):
+        """
+        Excludes all columns muxes unrelated to the target bit being simulated.
+        Each mux in mux_inst corresponds to respective column in bitcell array.
+        """
+        #stop = 34
+        for i in range(len(self.mux_inst)):
+            if i != column_include_num:
+                self.graph_inst_exclude.add(self.mux_inst[i])
+                debug.info(0, "Excluded mux {}".format(i))
+            #if i == stop:
+             #   break
\ No newline at end of file
diff --git a/compiler/modules/port_data.py b/compiler/modules/port_data.py
index 3fbb8696..b2490655 100644
--- a/compiler/modules/port_data.py
+++ b/compiler/modules/port_data.py
@@ -856,3 +856,10 @@ class port_data(design.design):
         """Precharge adds a loop between bitlines, can be excluded to reduce complexity"""
         if self.precharge_array_inst:
             self.graph_inst_exclude.add(self.precharge_array_inst)
+
+    def graph_exclude_column_mux(self, column_include_num):
+        """
+        Excludes all columns muxes unrelated to the target bit being simulated.
+        """
+        if self.column_mux_array:
+            self.column_mux_array.graph_exclude_columns(column_include_num)
\ No newline at end of file
diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py
index 828edfdd..0c911e51 100644
--- a/compiler/sram/sram_1bank.py
+++ b/compiler/sram/sram_1bank.py
@@ -637,7 +637,7 @@ class sram_1bank(sram_base):
         # Insts located in control logic, exclusion function called here
         for inst in self.control_logic_insts:
             inst.mod.graph_exclude_dffs()
-
+            
     def get_cell_name(self, inst_name, row, col):
         """
         Gets the spice name of the target bitcell.
diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py
index 01cf65b7..b396c745 100644
--- a/compiler/sram/sram_base.py
+++ b/compiler/sram/sram_base.py
@@ -773,3 +773,10 @@ class sram_base(design, verilog, lef):
         Clears the bit exclusions
         """
         self.bank.clear_exclude_bits()
+        
+    def graph_exclude_column_mux(self, column_include_num, port):
+        """
+        Excludes all columns muxes unrelated to the target bit being simulated.
+        """
+        self.bank.graph_exclude_column_mux(column_include_num, port)
+