mirror of
https://github.com/VLSIDA/OpenRAM.git
synced 2026-09-02 21:39:03 +02:00
Updates to local and global arrays to make bitline and wordlines consistent.
This commit is contained in:
mrg
@@ -21,39 +21,37 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
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Requires a regular bitcell array, replica bitcell, and dummy
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bitcell (Bl/BR disconnected).
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"""
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def __init__(self, rows, cols, rbl, name, add_rbl=None):
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def __init__(self, rows, cols, rbl, name, left_rbl=[], right_rbl=[]):
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super().__init__(name, rows, cols, column_offset=0)
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debug.info(1, "Creating {0} {1} x {2}".format(self.name, rows, cols))
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debug.info(1, "Creating {0} {1} x {2} rbls: {3} left_rbl: {4} right_rbl: {5}".format(self.name,
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rows,
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cols,
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rbl,
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left_rbl,
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right_rbl))
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self.add_comment("rows: {0} cols: {1}".format(rows, cols))
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self.add_comment("rbl: {0} left_rbl: {1} right_rbl: {2}".format(rbl, left_rbl, right_rbl))
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self.column_size = cols
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self.row_size = rows
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# This is how many RBLs are in all the arrays
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self.rbl = rbl
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self.left_rbl = rbl[0]
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self.right_rbl = rbl[1]
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# This is how many RBLs are added to THIS array
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if add_rbl == None:
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self.add_left_rbl = rbl[0]
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self.add_right_rbl = rbl[1]
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else:
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self.add_left_rbl = add_rbl[0]
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self.add_right_rbl = add_rbl[1]
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for a, b in zip(add_rbl, rbl):
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debug.check(a <= b,
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"Invalid number of RBLs for port configuration.")
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debug.check(sum(rbl) <= len(self.all_ports),
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# This specifies which RBL to put on the left or right
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# by port number
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self.left_rbl = left_rbl
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self.right_rbl = right_rbl
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self.rbls = self.left_rbl + self.right_rbl
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debug.check(sum(rbl) == len(self.all_ports),
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"Invalid number of RBLs for port configuration.")
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debug.check(sum(rbl) >= len(self.left_rbl) + len(self.right_rbl),
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"Invalid number of RBLs for port configuration.")
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# Two dummy rows plus replica even if we don't add the column
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self.extra_rows = 2 + sum(rbl)
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# Two dummy cols plus replica if we add the column
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self.extra_cols = 2 + self.add_left_rbl + self.add_right_rbl
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self.extra_cols = 2 + len(self.left_rbl) + len(self.right_rbl)
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self.create_all_bitline_names()
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self.create_all_wordline_names()
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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@@ -94,37 +92,45 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
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# Bitcell array
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self.bitcell_array = factory.create(module_type="bitcell_array",
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column_offset=1 + self.add_left_rbl,
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column_offset=1 + len(self.left_rbl),
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cols=self.column_size,
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rows=self.row_size)
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self.add_mod(self.bitcell_array)
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# Replica bitlines
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self.replica_columns = {}
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for bit in range(self.add_left_rbl + self.add_right_rbl):
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# Creating left_rbl
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if bit < self.add_left_rbl:
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for port in self.all_ports:
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if port in self.left_rbl:
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# We will always have self.rbl[0] rows of replica wordlines below
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# the array.
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# These go from the top (where the bitcell array starts ) down
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replica_bit = self.left_rbl - bit
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# Creating right_rbl
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else:
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replica_bit = self.rbl[0] - port
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elif port in self.right_rbl:
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# We will always have self.rbl[0] rows of replica wordlines below
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# the array.
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# These go from the bottom up
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replica_bit = self.left_rbl + self.row_size + 1 + bit
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replica_bit = self.rbl[0] + self.row_size + 1 + port
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else:
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continue
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# If we have an odd numer on the bottom
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column_offset = self.left_rbl + 1
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self.replica_columns[bit] = factory.create(module_type="replica_column",
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rows=self.row_size,
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rbl=self.rbl,
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column_offset=column_offset,
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replica_bit=replica_bit)
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self.add_mod(self.replica_columns[bit])
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column_offset = self.rbl[0] + 1
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self.replica_columns[port] = factory.create(module_type="replica_column",
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rows=self.row_size,
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rbl=self.rbl,
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column_offset=column_offset,
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replica_bit=replica_bit)
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self.add_mod(self.replica_columns[port])
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# Dummy row
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self.dummy_row = factory.create(module_type="dummy_array",
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cols=self.column_size,
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rows=1,
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# dummy column + left replica column
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column_offset=1 + self.add_left_rbl,
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column_offset=1 + len(self.left_rbl),
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mirror=0)
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self.add_mod(self.dummy_row)
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@@ -140,7 +146,7 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
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cols=self.column_size,
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rows=1,
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# dummy column + left replica column(s)
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column_offset=1 + self.add_left_rbl,
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column_offset=1 + len(self.left_rbl),
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mirror=0)
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self.add_mod(self.col_cap)
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@@ -151,7 +157,7 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
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cols=1,
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column_offset=0,
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rows=self.row_size + self.extra_rows,
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mirror=(self.left_rbl + 1) % 2)
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mirror=(self.rbl[0] + 1) % 2)
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self.add_mod(self.row_cap_left)
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self.row_cap_right = factory.create(module_type=row_cap_module_type,
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@@ -160,9 +166,9 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
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# + left replica column(s)
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# + bitcell columns
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# + right replica column(s)
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column_offset = 1 + self.add_left_rbl + self.column_size + self.add_right_rbl,
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column_offset = 1 + len(self.left_rbl) + self.column_size + len(self.right_rbl),
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rows=self.row_size + self.extra_rows,
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mirror=(self.left_rbl + 1) %2)
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mirror=(self.rbl[0] + 1) %2)
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self.add_mod(self.row_cap_right)
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def add_pins(self):
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@@ -186,73 +192,55 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
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self.add_pin("gnd", "GROUND")
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def add_bitline_pins(self):
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# Regular bitline names by port
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self.bitline_names = []
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# Replica bitlines by port
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self.rbl_bitline_names = []
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for x in range(self.add_left_rbl + self.add_right_rbl):
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self.rbl_bitline_names.append([])
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# The bit is which port the RBL is for
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for bit in self.rbls:
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for port in self.all_ports:
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self.rbl_bitline_names[-1].append("rbl_bl_{0}_{1}".format(port, x))
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for port in self.all_ports:
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self.rbl_bitline_names[-1].append("rbl_br_{0}_{1}".format(port, x))
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self.rbl_bitline_names[bit].append("rbl_bl_{0}_{1}".format(port, bit))
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self.rbl_bitline_names[bit].append("rbl_br_{0}_{1}".format(port, bit))
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# Make a flat list too
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self.all_rbl_bitline_names = [x for sl in self.rbl_bitline_names for x in sl]
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for port in self.all_ports:
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bitline_names = self.bitcell_array.get_bitline_names(port)
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self.bitline_names.append(bitline_names)
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self.bitline_names = self.bitcell_array.bitline_names
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# Make a flat list too
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self.all_bitline_names = [x for sl in zip(*self.bitline_names) for x in sl]
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for port in range(self.add_left_rbl):
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for port in self.left_rbl:
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self.add_pin_list(self.rbl_bitline_names[port], "INOUT")
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self.add_pin_list(self.all_bitline_names, "INOUT")
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for port in range(self.add_left_rbl, self.add_left_rbl + self.add_right_rbl):
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for port in self.right_rbl:
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self.add_pin_list(self.rbl_bitline_names[port], "INOUT")
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def add_wordline_pins(self):
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# Regular wordlines by port
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self.wordline_names = []
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# Replica wordlines by port
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self.rbl_wordline_names = []
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# Wordlines to ground
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self.gnd_wordline_names = []
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self.dummy_row_wordline_names = ["gnd"] * len(self.col_cap.get_wordline_names())
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for port in range(self.left_rbl + self.right_rbl):
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self.rbl_wordline_names.append([])
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for x in self.all_ports:
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self.rbl_wordline_names[-1].append("rbl_wl_{0}_{1}".format(x, port))
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if x != port:
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self.gnd_wordline_names.append("rbl_wl_{0}_{1}".format(x, port))
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for port in self.all_ports:
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for bit in self.all_ports:
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self.rbl_wordline_names[port].append("rbl_wl_{0}_{1}".format(port, bit))
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if bit != port:
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self.gnd_wordline_names.append("rbl_wl_{0}_{1}".format(port, bit))
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self.all_rbl_wordline_names = [x for sl in self.rbl_wordline_names for x in sl]
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for port in self.all_ports:
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wordline_names = self.bitcell_array.get_wordline_names(port)
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self.wordline_names.append(wordline_names)
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self.all_wordline_names = [x for sl in zip(*self.wordline_names) for x in sl]
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self.wordline_names = self.bitcell_array.wordline_names
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self.all_wordline_names = self.bitcell_array.all_wordline_names
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# All wordlines including dummy and RBL
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self.replica_array_wordline_names = []
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self.replica_array_wordline_names.extend(self.dummy_row_wordline_names)
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for p in range(self.left_rbl):
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self.replica_array_wordline_names.extend([x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[p]])
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self.replica_array_wordline_names.extend(["gnd"] * len(self.col_cap.get_wordline_names()))
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for bit in range(self.rbl[0]):
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self.replica_array_wordline_names.extend([x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[bit]])
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self.replica_array_wordline_names.extend(self.all_wordline_names)
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for p in range(self.left_rbl, self.left_rbl + self.right_rbl):
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self.replica_array_wordline_names.extend([x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[p]])
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self.replica_array_wordline_names.extend(self.dummy_row_wordline_names)
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for bit in range(self.rbl[1]):
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self.replica_array_wordline_names.extend([x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[self.rbl[0] + bit]])
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self.replica_array_wordline_names.extend(["gnd"] * len(self.col_cap.get_wordline_names()))
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for port in range(self.left_rbl):
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self.add_pin(self.rbl_wordline_names[port][0], "INPUT")
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for port in range(self.rbl[0]):
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self.add_pin(self.rbl_wordline_names[port][port], "INPUT")
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self.add_pin_list(self.all_wordline_names, "INPUT")
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for port in range(self.left_rbl, self.left_rbl + self.right_rbl):
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self.add_pin(self.rbl_wordline_names[port][1], "INPUT")
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for port in range(self.rbl[0], self.rbl[0] + self.rbl[1]):
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self.add_pin(self.rbl_wordline_names[port][port], "INPUT")
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def create_instances(self):
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""" Create the module instances used in this design """
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@@ -269,27 +257,30 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
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# Replica columns
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self.replica_col_insts = []
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for port in range(self.add_left_rbl + self.add_right_rbl):
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self.replica_col_insts.append(self.add_inst(name="replica_col_{}".format(port),
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mod=self.replica_columns[port]))
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self.connect_inst(self.rbl_bitline_names[port] + self.replica_array_wordline_names + supplies)
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for port in self.all_ports:
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if port in self.rbls:
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self.replica_col_insts.append(self.add_inst(name="replica_col_{}".format(port),
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mod=self.replica_columns[port]))
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self.connect_inst(self.rbl_bitline_names[port] + self.replica_array_wordline_names + supplies)
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else:
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self.replica_col_insts.append(None)
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# Dummy rows under the bitcell array (connected with with the replica cell wl)
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self.dummy_row_replica_insts = []
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# Note, this is the number of left and right even if we aren't adding the columns to this bitcell array!
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for port in range(self.left_rbl + self.right_rbl):
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for port in self.all_ports:
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self.dummy_row_replica_insts.append(self.add_inst(name="dummy_row_{}".format(port),
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mod=self.dummy_row))
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mod=self.dummy_row))
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self.connect_inst([x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[port]] + supplies)
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# Top/bottom dummy rows or col caps
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self.dummy_row_insts = []
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self.dummy_row_insts.append(self.add_inst(name="dummy_row_bot",
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mod=self.col_cap))
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self.connect_inst(self.dummy_row_wordline_names + supplies)
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mod=self.col_cap))
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self.connect_inst(["gnd"] * len(self.col_cap.get_wordline_names()) + supplies)
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self.dummy_row_insts.append(self.add_inst(name="dummy_row_top",
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mod=self.col_cap))
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self.connect_inst(self.dummy_row_wordline_names + supplies)
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self.connect_inst(["gnd"] * len(self.col_cap.get_wordline_names()) + supplies)
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# Left/right Dummy columns
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self.dummy_col_insts = []
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@@ -318,7 +309,7 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
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# Array was at (0, 0) but move everything so it is at the lower left
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# We move DOWN the number of left RBL even if we didn't add the column to this bitcell array
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self.translate_all(self.bitcell_offset.scale(-1 - self.add_left_rbl, -1 - self.left_rbl))
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self.translate_all(self.bitcell_offset.scale(-1 - len(self.left_rbl), -1 - self.rbl[0]))
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self.add_layout_pins()
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@@ -332,47 +323,47 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
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""" Add replica columns on left and right of array """
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# Grow from left to right, toward the array
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for bit in range(self.add_left_rbl):
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offset = self.bitcell_offset.scale(-self.add_left_rbl + bit, -self.left_rbl - 1)
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self.replica_col_insts[bit].place(offset)
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for bit, port in enumerate(self.left_rbl):
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offset = self.bitcell_offset.scale(-len(self.left_rbl) + bit, -self.rbl[0] - 1)
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self.replica_col_insts[port].place(offset)
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# Grow to the right of the bitcell array, array outward
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for bit in range(self.add_right_rbl):
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offset = self.bitcell_array_inst.lr() + self.bitcell_offset.scale(bit, -self.left_rbl - 1)
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self.replica_col_insts[self.add_left_rbl + bit].place(offset)
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for bit, port in enumerate(self.right_rbl):
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offset = self.bitcell_array_inst.lr() + self.bitcell_offset.scale(bit, -self.rbl[0] - 1)
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self.replica_col_insts[port].place(offset)
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# Replica dummy rows
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# Add the dummy rows even if we aren't adding the replica column to this bitcell array
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# These grow up, toward the array
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for bit in range(self.left_rbl):
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self.dummy_row_replica_insts[bit].place(offset=self.bitcell_offset.scale(0, -self.left_rbl + bit + (-self.left_rbl + bit) % 2),
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mirror="MX" if (-self.left_rbl + bit) % 2 else "R0")
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for bit in range(self.rbl[0]):
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self.dummy_row_replica_insts[bit].place(offset=self.bitcell_offset.scale(0, -self.rbl[0] + bit + (-self.rbl[0] + bit) % 2),
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mirror="MX" if (-self.rbl[0] + bit) % 2 else "R0")
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# These grow up, away from the array
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for bit in range(self.right_rbl):
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self.dummy_row_replica_insts[self.left_rbl + bit].place(offset=self.bitcell_offset.scale(0, bit + bit % 2) + self.bitcell_array_inst.ul(),
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mirror="MX" if bit % 2 else "R0")
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for bit in range(self.rbl[1]):
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self.dummy_row_replica_insts[self.rbl[0] + bit].place(offset=self.bitcell_offset.scale(0, bit + bit % 2) + self.bitcell_array_inst.ul(),
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mirror="MX" if bit % 2 else "R0")
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def add_end_caps(self):
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""" Add dummy cells or end caps around the array """
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# FIXME: These depend on the array size itself
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# Far top dummy row (first row above array is NOT flipped)
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flip_dummy = self.right_rbl % 2
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dummy_row_offset = self.bitcell_offset.scale(0, self.right_rbl + flip_dummy) + self.bitcell_array_inst.ul()
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flip_dummy = self.rbl[1] % 2
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dummy_row_offset = self.bitcell_offset.scale(0, self.rbl[1] + flip_dummy) + self.bitcell_array_inst.ul()
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self.dummy_row_insts[1].place(offset=dummy_row_offset,
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mirror="MX" if flip_dummy else "R0")
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# FIXME: These depend on the array size itself
|
||||
# Far bottom dummy row (first row below array IS flipped)
|
||||
flip_dummy = (self.left_rbl + 1) % 2
|
||||
dummy_row_offset = self.bitcell_offset.scale(0, -self.left_rbl - 1 + flip_dummy)
|
||||
flip_dummy = (self.rbl[0] + 1) % 2
|
||||
dummy_row_offset = self.bitcell_offset.scale(0, -self.rbl[0] - 1 + flip_dummy)
|
||||
self.dummy_row_insts[0].place(offset=dummy_row_offset,
|
||||
mirror="MX" if flip_dummy else "R0")
|
||||
# Far left dummy col
|
||||
# Shifted down by the number of left RBLs even if we aren't adding replica column to this bitcell array
|
||||
dummy_col_offset = self.bitcell_offset.scale(-self.add_left_rbl - 1, -self.left_rbl - 1)
|
||||
dummy_col_offset = self.bitcell_offset.scale(-len(self.left_rbl) - 1, -self.rbl[0] - 1)
|
||||
self.dummy_col_insts[0].place(offset=dummy_col_offset)
|
||||
# Far right dummy col
|
||||
# Shifted down by the number of left RBLs even if we aren't adding replica column to this bitcell array
|
||||
dummy_col_offset = self.bitcell_offset.scale(self.add_right_rbl, -self.left_rbl - 1) + self.bitcell_array_inst.lr()
|
||||
dummy_col_offset = self.bitcell_offset.scale(len(self.right_rbl), -self.rbl[0] - 1) + self.bitcell_array_inst.lr()
|
||||
self.dummy_col_insts[1].place(offset=dummy_col_offset)
|
||||
|
||||
def add_layout_pins(self):
|
||||
@@ -412,14 +403,15 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
|
||||
height=pin.height())
|
||||
|
||||
# Replica bitlines
|
||||
for (names, inst) in zip(self.rbl_bitline_names, self.replica_col_insts):
|
||||
for (bl_name, pin_name) in zip(names, self.replica_columns[0].all_bitline_names):
|
||||
pin = inst.get_pin(pin_name)
|
||||
self.add_layout_pin(text=bl_name,
|
||||
layer=pin.layer,
|
||||
offset=pin.ll().scale(1, 0),
|
||||
width=pin.width(),
|
||||
height=self.height)
|
||||
if len(self.rbls) > 0:
|
||||
for (names, inst) in zip(self.rbl_bitline_names, self.replica_col_insts):
|
||||
for (bl_name, pin_name) in zip(names, self.replica_columns[self.rbls[0]].all_bitline_names):
|
||||
pin = inst.get_pin(pin_name)
|
||||
self.add_layout_pin(text=bl_name,
|
||||
layer=pin.layer,
|
||||
offset=pin.ll().scale(1, 0),
|
||||
width=pin.width(),
|
||||
height=self.height)
|
||||
|
||||
# vdd/gnd are only connected in the perimeter cells
|
||||
# replica column should only have a vdd/gnd in the dummy cell on top/bottom
|
||||
@@ -434,7 +426,8 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
|
||||
start_layer=pin.layer)
|
||||
|
||||
for inst in self.replica_col_insts:
|
||||
self.copy_layout_pin(inst, pin_name)
|
||||
if inst:
|
||||
self.copy_layout_pin(inst, pin_name)
|
||||
|
||||
def analytical_power(self, corner, load):
|
||||
"""Power of Bitcell array and bitline in nW."""
|
||||
|
||||
Reference in New Issue
Block a user