From 7bb21fb73f39322826a0e9de5f2bcb83c0c0651c Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 9 Sep 2020 11:54:46 -0700 Subject: [PATCH] Updates to local and global arrays to make bitline and wordlines consistent. --- compiler/modules/bank.py | 23 +- compiler/modules/bitcell_array.py | 9 +- compiler/modules/bitcell_base_array.py | 44 ++-- compiler/modules/dummy_array.py | 4 + compiler/modules/global_bitcell_array.py | 84 +++---- compiler/modules/local_bitcell_array.py | 143 +++++++---- compiler/modules/replica_bitcell_array.py | 231 +++++++++--------- .../14_replica_bitcell_array_1rw_1r_test.py | 11 +- .../15_local_bitcell_array_1rw_1r_test.py | 15 +- compiler/tests/15_local_bitcell_array_test.py | 4 +- 10 files changed, 304 insertions(+), 264 deletions(-) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index fb909465..57b3f383 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -392,7 +392,9 @@ class bank(design.design): self.bitcell_array = factory.create(module_type="replica_bitcell_array", cols=self.num_cols + self.num_spare_cols, rows=self.num_rows, - rbl=[1, 1 if len(self.all_ports)>1 else 0]) + rbl=[1, 1 if len(self.all_ports)>1 else 0], + left_rbl=[0], + right_rbl=[1] if len(self.all_ports) > 1 else []) self.add_mod(self.bitcell_array) if(self.num_banks > 1): @@ -408,19 +410,14 @@ class bank(design.design): # bit lines (left to right) # vdd # gnd - import pdb; pdb.set_trace() - temp = self.bitcell_array.get_all_bitline_names() + temp = self.bitcell_array.get_inouts() - wordline_names = self.bitcell_array.get_all_wordline_names() + wordline_names = self.bitcell_array.get_inputs() # Rename the RBL WL to the enable name for port in self.all_ports: - rbl_wl_name = self.bitcell_array.get_rbl_wordline_names(port) - wordline_names = [x.replace(rbl_wl_name[port], "wl_en{0}".format(port)) for x in wordline_names] - # Connect the other RBL WL to gnd - wordline_names = ["gnd" if x.startswith("rbl_wl") else x for x in wordline_names] - # Connect the dummy WL to gnd - wordline_names = ["gnd" if x.startswith("dummy") else x for x in wordline_names] + rbl_wl_name = self.bitcell_array.get_rbl_wordline_names(port)[port] + wordline_names = [x.replace(rbl_wl_name, "wl_en{0}".format(port)) for x in wordline_names] temp.extend(wordline_names) temp.append("vdd") @@ -439,7 +436,6 @@ class bank(design.design): for port in self.all_ports: self.port_data_inst[port]=self.add_inst(name="port_data{}".format(port), mod=self.port_data[port]) - import pdb; pdb.set_trace() temp = [] temp.extend(["rbl_bl_{0}_{0}".format(port), "rbl_br_{0}_{0}".format(port)]) temp.extend(self.bitcell_array.get_bitline_names(port)) @@ -978,16 +974,15 @@ class bank(design.design): def route_unused_wordlines(self): """ Connect the unused RBL and dummy wordlines to gnd """ gnd_wl_names = [] - + return # Connect unused RBL WL to gnd # All RBL WL names array_rbl_names = set(self.bitcell_array.get_rbl_wordline_names()) - dummy_rbl_names = set(self.bitcell_array.get_dummy_wordline_names()) # List of used RBL WL names rbl_wl_names = set() for port in self.all_ports: rbl_wl_names.add(self.bitcell_array.get_rbl_wordline_names(port)[port]) - gnd_wl_names = list((array_rbl_names - rbl_wl_names) | dummy_rbl_names) + gnd_wl_names = list((array_rbl_names - rbl_wl_names)) for wl_name in gnd_wl_names: pin = self.bitcell_array_inst.get_pin(wl_name) diff --git a/compiler/modules/bitcell_array.py b/compiler/modules/bitcell_array.py index 81f1062f..a5d09ab6 100644 --- a/compiler/modules/bitcell_array.py +++ b/compiler/modules/bitcell_array.py @@ -5,6 +5,7 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import debug from bitcell_base_array import bitcell_base_array from tech import drc, spice from globals import OPTS @@ -18,11 +19,17 @@ class bitcell_array(bitcell_base_array): """ def __init__(self, rows, cols, column_offset=0, name=""): super().__init__(rows=rows, cols=cols, column_offset=column_offset, name=name) + debug.info(1, "Creating {0} {1} x {2}".format(self.name, rows, cols)) + self.add_comment("rows: {0} cols: {1}".format(rows, cols)) + # This will create a default set of bitline/wordline names + self.create_all_bitline_names() + self.create_all_wordline_names() + self.create_netlist() if not OPTS.netlist_only: self.create_layout() - + # We don't offset this because we need to align # the replica bitcell in the control logic # self.offset_all_coordinates() diff --git a/compiler/modules/bitcell_base_array.py b/compiler/modules/bitcell_base_array.py index 9f27f5b4..91363560 100644 --- a/compiler/modules/bitcell_base_array.py +++ b/compiler/modules/bitcell_base_array.py @@ -18,7 +18,6 @@ class bitcell_base_array(design.design): def __init__(self, name, rows, cols, column_offset): super().__init__(name) debug.info(1, "Creating {0} {1} x {2}".format(self.name, rows, cols)) - self.add_comment("rows: {0} cols: {1}".format(rows, cols)) self.column_size = cols self.row_size = rows @@ -27,13 +26,16 @@ class bitcell_base_array(design.design): # Bitcell for port names only self.cell = factory.create(module_type="bitcell") - # This will create a default set of bitline/wordline names - # They may get over-riden in the super module - self.create_all_bitline_names() - self.create_all_wordline_names() + self.wordline_names = [[] for port in self.all_ports] + self.all_wordline_names = [] + self.bitline_names = [[] for port in self.all_ports] + self.all_bitline_names = [] + self.rbl_bitline_names = [[] for port in self.all_ports] + self.all_rbl_bitline_names = [] + self.rbl_wordline_names = [[] for port in self.all_ports] + self.all_rbl_wordline_names = [] def create_all_bitline_names(self): - self.bitline_names = [[] for port in self.all_ports] for col in range(self.column_size): for port in self.all_ports: self.bitline_names[port].extend(["bl_{0}_{1}".format(port, col), @@ -45,7 +47,6 @@ class bitcell_base_array(design.design): # return [prefix + x for x in self.all_wordline_names] def create_all_wordline_names(self): - self.wordline_names = [[] for port in self.all_ports] for row in range(self.row_size): for port in self.all_ports: self.wordline_names[port].append("wl_{0}_{1}".format(port, row)) @@ -73,8 +74,7 @@ class bitcell_base_array(design.design): def get_rbl_wordline_names(self, port=None): """ - Return the ACTIVE WL for the given RBL port. - Inactive will be set to gnd. + Return the WL for the given RBL port. """ if port == None: return self.all_rbl_wordline_names @@ -82,7 +82,7 @@ class bitcell_base_array(design.design): return self.rbl_wordline_names[port] def get_rbl_bitline_names(self, port=None): - """ Return the BL for the given RBL port """ + """ Return all the BL for the given RBL port """ if port == None: return self.all_rbl_bitline_names else: @@ -95,14 +95,16 @@ class bitcell_base_array(design.design): else: return self.bitline_names[port] - def get_all_bitline_names(self): - """ Return ALL the bitline names (including dummy and rbl) """ + def get_all_bitline_names(self, port=None): + """ Return ALL the bitline names (including rbl) """ temp = [] - if self.add_left_rbl > 0: - temp.extend(self.get_rbl_bitline_names(0)) - temp.extend(self.get_bitline_names()) - if self.add_right_rbl > 0: - temp.extend(self.get_rbl_bitline_names(self.add_left_rbl)) + temp.extend(self.get_rbl_bitline_names(0)) + if port == None: + temp.extend(self.all_bitline_names) + else: + temp.extend(self.bitline_names[port]) + if len(self.all_ports) > 1: + temp.extend(self.get_rbl_bitline_names(1)) return temp def get_wordline_names(self, port=None): @@ -115,7 +117,6 @@ class bitcell_base_array(design.design): def get_all_wordline_names(self, port=None): """ Return all the wordline names """ temp = [] - temp.extend(self.get_dummy_wordline_names()) temp.extend(self.get_rbl_wordline_names(0)) if port == None: temp.extend(self.all_wordline_names) @@ -123,15 +124,8 @@ class bitcell_base_array(design.design): temp.extend(self.wordline_names[port]) if len(self.all_ports) > 1: temp.extend(self.get_rbl_wordline_names(1)) - temp.extend(self.get_dummy_wordline_names()) return temp - def get_dummy_wordline_names(self): - """ - Return the ACTIVE WL for the given dummy port. - """ - return self.dummy_row_wordline_names - def add_layout_pins(self): """ Add the layout pins """ diff --git a/compiler/modules/dummy_array.py b/compiler/modules/dummy_array.py index 37ce0ba4..0fd7d648 100644 --- a/compiler/modules/dummy_array.py +++ b/compiler/modules/dummy_array.py @@ -16,6 +16,10 @@ class dummy_array(bitcell_base_array): super().__init__(rows=rows, cols=cols, column_offset=column_offset, name=name) self.mirror = mirror + # This will create a default set of bitline/wordline names + self.create_all_bitline_names() + self.create_all_wordline_names() + self.create_netlist() if not OPTS.netlist_only: self.create_layout() diff --git a/compiler/modules/global_bitcell_array.py b/compiler/modules/global_bitcell_array.py index 319a85cc..fa2718bc 100644 --- a/compiler/modules/global_bitcell_array.py +++ b/compiler/modules/global_bitcell_array.py @@ -18,7 +18,6 @@ class global_bitcell_array(bitcell_base_array.bitcell_base_array): Creates a global bitcell array. Rows is an integer number for all local arrays. Cols is a list of the array widths. - add_left_rbl and add_right_ """ def __init__(self, rows, cols, name=""): # The total of all columns will be the number of columns @@ -28,8 +27,6 @@ class global_bitcell_array(bitcell_base_array.bitcell_base_array): debug.check(len(self.all_ports)<=2, "Only support dual port or less in global bitcell array.") self.rbl = [1, 1 if len(self.all_ports)>1 else 0] - self.add_left_rbl = self.rbl[0] - self.add_right_rbl = self.rbl[1] self.create_netlist() if not OPTS.netlist_only: @@ -58,19 +55,35 @@ class global_bitcell_array(bitcell_base_array.bitcell_base_array): self.local_mods = [] if len(self.column_sizes) == 1: - la = factory.create(module_type="local_bitcell_array", rows=self.row_size, cols=self.column_sizes[0], rbl=self.rbl, add_rbl=[self.add_left_rbl, self.add_right_rbl]) + la = factory.create(module_type="local_bitcell_array", + rows=self.row_size, + cols=self.column_sizes[0], + rbl=self.rbl, + left_rbl=[0], + right_rbl=[1]) self.add_mod(la) self.local_mods.append(la) return - + for i, cols in enumerate(self.column_sizes): # Always add the left RBLs to the first subarray and the right RBLs to the last subarray if i == 0: - la = factory.create(module_type="local_bitcell_array", rows=self.row_size, cols=cols, rbl=self.rbl, add_rbl=[self.add_left_rbl, 0]) - elif i == len(self.column_sizes) - 1: - la = factory.create(module_type="local_bitcell_array", rows=self.row_size, cols=cols, rbl=self.rbl, add_rbl=[0, self.add_right_rbl]) + la = factory.create(module_type="local_bitcell_array", + rows=self.row_size, + cols=cols, + rbl=self.rbl, + left_rbl=[0]) + elif i == len(self.column_sizes) - 1 and len(self.all_ports) > 1: + la = factory.create(module_type="local_bitcell_array", + rows=self.row_size, + cols=cols, + rbl=self.rbl, + right_rbl=[1]) else: - la = factory.create(module_type="local_bitcell_array", rows=self.row_size, cols=cols, rbl=self.rbl, add_rbl=[0, 0]) + la = factory.create(module_type="local_bitcell_array", + rows=self.row_size, + cols=cols, + rbl=self.rbl) self.add_mod(la) self.local_mods.append(la) @@ -88,10 +101,8 @@ class global_bitcell_array(bitcell_base_array.bitcell_base_array): self.rbl_bitline_names = [[] for x in self.all_ports] for port in self.all_ports: - self.bitline_names[port].append("rbl_bl_{}_0".format(port)) self.rbl_bitline_names[port].append("rbl_bl_{}_0".format(port)) for port in self.all_ports: - self.bitline_names[port].append("rbl_br_{}_0".format(port)) self.rbl_bitline_names[port].append("rbl_br_{}_0".format(port)) for col in range(self.column_size): @@ -102,10 +113,8 @@ class global_bitcell_array(bitcell_base_array.bitcell_base_array): if len(self.all_ports) > 1: for port in self.all_ports: - self.bitline_names[port].append("rbl_bl_{}_1".format(port)) self.rbl_bitline_names[port].append("rbl_bl_{}_1".format(port)) for port in self.all_ports: - self.bitline_names[port].append("rbl_br_{}_1".format(port)) self.rbl_bitline_names[port].append("rbl_br_{}_1".format(port)) # Make a flat list too @@ -138,8 +147,6 @@ class global_bitcell_array(bitcell_base_array.bitcell_base_array): def create_instances(self): """ Create the module instances used in this design """ - - self.local_insts = [] for col, mod in zip(self.col_offsets, self.local_mods): name = "la_{0}".format(col) @@ -193,32 +200,8 @@ class global_bitcell_array(bitcell_base_array.bitcell_base_array): def route(self): - # Route the global wordlines (assumes pins all line up) - for port in self.all_ports: - port_inputs = [x for x in self.local_mods[0].get_inputs() if "wl_{}".format(port) in x] - for i, pin_name in enumerate(port_inputs): - pins = [x.get_pin(pin_name) for x in self.local_insts] - - y_offset = pins[0].cy() - if port == 0: - y_offset -= 1.5 * self.m3_pitch - else: - y_offset += 1.5 * self.m3_pitch - - start_offset = vector(pins[0].lx(), y_offset) - end_offset = vector(pins[-1].rx(), y_offset) - self.add_layout_pin_segment_center(text=pin_name, - layer="m3", - start=start_offset, - end=end_offset) - - for pin in pins: - self.add_via_stack_center(from_layer=pin.layer, - to_layer="m3", - offset=pin.center()) - end_offset = vector(pin.cx(), y_offset) - self.add_path("m3", [pin.center(), end_offset]) - + pass + def add_layout_pins(self): # Regular bitlines @@ -237,10 +220,13 @@ class global_bitcell_array(bitcell_base_array.bitcell_base_array): new_name = "{0}_{1}".format(base_name, col + col_value) self.copy_layout_pin(inst, pin_name, new_name) - # Replica wordlines - self.copy_layout_pin(self.local_insts[0], "rbl_wl_0_0") - if len(self.all_ports) > 1: - self.copy_layout_pin(self.local_insts[-1], "rbl_wl_1_1") + for wl_name in self.local_mods[0].get_inputs(): + left_pin = self.local_insts[0].get_pin(wl_name) + right_pin = self.local_insts[-1].get_pin(wl_name) + self.add_layout_pin_segment_center(text=wl_name, + layer=left_pin.layer, + start=left_pin.lc(), + end=right_pin.rc()) # Replica bitlines self.copy_layout_pin(self.local_insts[0], "rbl_bl_0_0") @@ -249,10 +235,10 @@ class global_bitcell_array(bitcell_base_array.bitcell_base_array): if len(self.all_ports) > 1: self.copy_layout_pin(self.local_insts[0], "rbl_bl_1_0") self.copy_layout_pin(self.local_insts[0], "rbl_br_1_0") - self.copy_layout_pin(self.local_insts[-1], "rbl_bl_0_0", "rbl_bl_0_1") - self.copy_layout_pin(self.local_insts[-1], "rbl_br_0_0", "rbl_br_0_1") - self.copy_layout_pin(self.local_insts[-1], "rbl_bl_1_0", "rbl_bl_1_1") - self.copy_layout_pin(self.local_insts[-1], "rbl_br_1_0", "rbl_br_1_1") + self.copy_layout_pin(self.local_insts[-1], "rbl_bl_0_1") + self.copy_layout_pin(self.local_insts[-1], "rbl_br_0_1") + self.copy_layout_pin(self.local_insts[-1], "rbl_bl_1_1") + self.copy_layout_pin(self.local_insts[-1], "rbl_br_1_1") for inst in self.insts: self.copy_power_pins(inst, "vdd") diff --git a/compiler/modules/local_bitcell_array.py b/compiler/modules/local_bitcell_array.py index d3881830..c805b9e4 100644 --- a/compiler/modules/local_bitcell_array.py +++ b/compiler/modules/local_bitcell_array.py @@ -18,18 +18,21 @@ class local_bitcell_array(bitcell_base_array.bitcell_base_array): This can either be a single aray on its own if there is no hierarchical WL or it can be combined into a larger array with hierarchical WL. """ - def __init__(self, rows, cols, rbl, add_rbl=None, name=""): + def __init__(self, rows, cols, rbl, left_rbl=[], right_rbl=[], name=""): super().__init__(name=name, rows=rows, cols=cols, column_offset=0) - debug.info(2, "create local array of size {} rows x {} cols words".format(rows, cols)) + debug.info(2, "Creating {0} {1}x{2} rbl: {3} left_rbl: {4} right_rbl: {5}".format(name, + rows, + cols, + rbl, + left_rbl, + right_rbl)) self.rows = rows self.cols = cols self.rbl = rbl - if add_rbl == None: - self.add_rbl = rbl - else: - self.add_rbl = add_rbl - + self.left_rbl = left_rbl + self.right_rbl = right_rbl + debug.check(len(self.all_ports) < 3, "Local bitcell array only supports dual port or less.") self.create_netlist() @@ -39,7 +42,7 @@ class local_bitcell_array(bitcell_base_array.bitcell_base_array): # We don't offset this because we need to align # the replica bitcell in the control logic # self.offset_all_coordinates() - + def create_netlist(self): """ Create and connect the netlist """ self.add_modules() @@ -67,53 +70,51 @@ class local_bitcell_array(bitcell_base_array.bitcell_base_array): cols=self.cols, rows=self.rows, rbl=self.rbl, - add_rbl=self.add_rbl) + left_rbl=self.left_rbl, + right_rbl=self.right_rbl) self.add_mod(self.bitcell_array) self.wl_array = factory.create(module_type="wordline_buffer_array", rows=self.rows + 1, cols=self.cols) self.add_mod(self.wl_array) - - # We make these on our own and don't use the base names - def create_all_wordline_names(self): - pass - - # We make these on our own and don't use the base names - def create_all_bitline_names(self): - pass def add_pins(self): - # Inputs to the wordline driver (by port) - self.wordline_names = [] # Outputs from the wordline driver (by port) self.driver_wordline_outputs = [] # Inputs to the bitcell array (by port) self.array_wordline_inputs = [] - for port in self.all_ports: - wordline_inputs = [] - if port == 0: - wordline_inputs += [self.bitcell_array.get_rbl_wordline_names(0)[0]] - wordline_inputs += self.bitcell_array.get_wordline_names(port) - if port == 1: - wordline_inputs += [self.bitcell_array.get_rbl_wordline_names(1)[1]] - self.wordline_names.append(wordline_inputs) - self.driver_wordline_outputs.append([x + "i" for x in self.wordline_names[-1]]) - - self.all_array_wordline_inputs = [x + "i" for x in self.bitcell_array.get_inputs() if "wl" in x] - + self.wordline_names = self.bitcell_array.wordline_names + self.all_wordline_names = self.bitcell_array.all_wordline_names + self.bitline_names = self.bitcell_array.bitline_names - self.all_array_bitline_names = self.bitcell_array.get_all_bitline_names() + self.all_bitline_names = self.bitcell_array.all_bitline_names + self.rbl_wordline_names = self.bitcell_array.rbl_wordline_names + self.all_rbl_wordline_names = self.bitcell_array.all_rbl_wordline_names + + self.rbl_bitline_names = self.bitcell_array.rbl_bitline_names + self.all_rbl_bitline_names = self.bitcell_array.all_rbl_bitline_names + + self.all_array_wordline_inputs = [x + "i" for x in self.bitcell_array.get_all_wordline_names()] + # Arrays are always: # bit lines (left to right) # word lines (bottom to top) # vdd # gnd - self.add_pin_list(self.all_array_bitline_names, "INOUT") + for port in self.left_rbl: + self.add_pin_list(self.rbl_bitline_names[port], "INOUT") + self.add_pin_list(self.all_bitline_names, "INOUT") + for port in self.right_rbl: + self.add_pin_list(self.rbl_bitline_names[port], "INOUT") + for port in range(self.rbl[0]): + self.add_pin(self.rbl_wordline_names[port][port], "INPUT") for port in self.all_ports: self.add_pin_list(self.wordline_names[port], "INPUT") + for port in range(self.rbl[0], self.rbl[0] + self.rbl[1]): + self.add_pin(self.rbl_wordline_names[port][port], "INPUT") self.add_pin("vdd", "POWER") self.add_pin("gnd", "GROUND") @@ -121,15 +122,41 @@ class local_bitcell_array(bitcell_base_array.bitcell_base_array): """ Create the module instances used in this design """ self.wl_insts = [] + self.driver_wordline_outputs = [] for port in self.all_ports: self.wl_insts.append(self.add_inst(name="wl_driver", mod=self.wl_array)) - self.connect_inst(self.wordline_names[port] + self.driver_wordline_outputs[port] + ["vdd", "gnd"]) + temp = [] + temp += [self.get_rbl_wordline_names(port)[port]] + if port == 0: + temp += self.get_wordline_names(port) + else: + temp += self.get_wordline_names(port)[::-1] + self.driver_wordline_outputs.append([x + "i" for x in temp]) + + temp += self.driver_wordline_outputs[-1] + temp += ["vdd", "gnd"] + + self.connect_inst(temp) self.bitcell_array_inst = self.add_inst(name="array", mod=self.bitcell_array) + temp = [] + for port in self.left_rbl: + temp += self.get_rbl_bitline_names(port) + temp += self.all_bitline_names + for port in self.right_rbl: + temp += self.get_rbl_bitline_names(port) - self.connect_inst(self.all_array_bitline_names + self.all_array_wordline_inputs + ["vdd", "gnd"]) + wl_temp = [] + for port in range(self.rbl[0]): + wl_temp += [self.get_rbl_wordline_names(port)[port]] + wl_temp += self.get_wordline_names() + for port in range(self.rbl[0], sum(self.rbl)): + wl_temp += [self.get_rbl_wordline_names(port)[port]] + temp += [x + "i" for x in wl_temp] + temp += ["vdd", "gnd"] + self.connect_inst(temp) def place(self): """ Place the bitcelll array to the right of the wl driver. """ @@ -143,8 +170,8 @@ class local_bitcell_array(bitcell_base_array.bitcell_base_array): if len(self.all_ports) > 1: self.wl_insts[1].place(vector(self.bitcell_array_inst.rx() + self.wl_array.width + driver_to_array_spacing, - 2 * self.cell.height), - mirror="MY") + 2 * self.cell.height + self.wl_array.height), + mirror="XY") self.height = self.bitcell_array.height self.width = max(self.bitcell_array_inst.rx(), max([x.rx() for x in self.wl_insts])) @@ -154,10 +181,6 @@ class local_bitcell_array(bitcell_base_array.bitcell_base_array): for x in self.get_inouts(): self.copy_layout_pin(self.bitcell_array_inst, x) - for port in self.all_ports: - for (x, y) in zip(self.wordline_names[port], self.wl_array.get_inputs()): - self.copy_layout_pin(self.wl_insts[port], y, x) - supply_insts = [*self.wl_insts, self.bitcell_array_inst] for pin_name in ["vdd", "gnd"]: for inst in supply_insts: @@ -169,8 +192,44 @@ class local_bitcell_array(bitcell_base_array.bitcell_base_array): def route(self): + # Route the global wordlines for port in self.all_ports: - for (driver_name, net_name) in zip(self.wl_insts[port].mod.get_outputs(), self.driver_wordline_outputs[port]): + if port == 0: + wordline_names = [self.get_rbl_wordline_names(port)[port]] + self.get_wordline_names(port) + else: + wordline_names = [self.get_rbl_wordline_names(port)[port]] + self.get_wordline_names(port)[::-1] + + wordline_pins = self.wl_array.get_inputs() + + for (wl_name, in_pin_name) in zip(wordline_names, wordline_pins): + # wl_pin = self.bitcell_array_inst.get_pin(wl_name) + in_pin = self.wl_insts[port].get_pin(in_pin_name) + + y_offset = in_pin.cy() + if port == 0: + y_offset -= 1.5 * self.m3_pitch + else: + y_offset += 1.5 * self.m3_pitch + + self.add_layout_pin_segment_center(text=wl_name, + layer="m3", + start=vector(0, y_offset), + end=vector(self.width, y_offset)) + + mid = vector(in_pin.cx(), y_offset) + self.add_path("m2", [in_pin.center(), mid]) + + self.add_via_stack_center(from_layer=in_pin.layer, + to_layer="m2", + offset=in_pin.center()) + self.add_via_center(self.m2_stack, + offset=mid) + + # Route the buffers + for port in self.all_ports: + driver_outputs = self.driver_wordline_outputs[port] + + for (driver_name, net_name) in zip(self.wl_insts[port].mod.get_outputs(), driver_outputs): array_name = net_name[:-1] out_pin = self.wl_insts[port].get_pin(driver_name) in_pin = self.bitcell_array_inst.get_pin(array_name) diff --git a/compiler/modules/replica_bitcell_array.py b/compiler/modules/replica_bitcell_array.py index efbc14cf..0091c20b 100644 --- a/compiler/modules/replica_bitcell_array.py +++ b/compiler/modules/replica_bitcell_array.py @@ -21,39 +21,37 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array): Requires a regular bitcell array, replica bitcell, and dummy bitcell (Bl/BR disconnected). """ - def __init__(self, rows, cols, rbl, name, add_rbl=None): + def __init__(self, rows, cols, rbl, name, left_rbl=[], right_rbl=[]): super().__init__(name, rows, cols, column_offset=0) - debug.info(1, "Creating {0} {1} x {2}".format(self.name, rows, cols)) + debug.info(1, "Creating {0} {1} x {2} rbls: {3} left_rbl: {4} right_rbl: {5}".format(self.name, + rows, + cols, + rbl, + left_rbl, + right_rbl)) self.add_comment("rows: {0} cols: {1}".format(rows, cols)) + self.add_comment("rbl: {0} left_rbl: {1} right_rbl: {2}".format(rbl, left_rbl, right_rbl)) self.column_size = cols self.row_size = rows # This is how many RBLs are in all the arrays self.rbl = rbl - self.left_rbl = rbl[0] - self.right_rbl = rbl[1] - # This is how many RBLs are added to THIS array - if add_rbl == None: - self.add_left_rbl = rbl[0] - self.add_right_rbl = rbl[1] - else: - self.add_left_rbl = add_rbl[0] - self.add_right_rbl = add_rbl[1] - for a, b in zip(add_rbl, rbl): - debug.check(a <= b, - "Invalid number of RBLs for port configuration.") - - debug.check(sum(rbl) <= len(self.all_ports), + # This specifies which RBL to put on the left or right + # by port number + self.left_rbl = left_rbl + self.right_rbl = right_rbl + self.rbls = self.left_rbl + self.right_rbl + + debug.check(sum(rbl) == len(self.all_ports), + "Invalid number of RBLs for port configuration.") + debug.check(sum(rbl) >= len(self.left_rbl) + len(self.right_rbl), "Invalid number of RBLs for port configuration.") # Two dummy rows plus replica even if we don't add the column self.extra_rows = 2 + sum(rbl) # Two dummy cols plus replica if we add the column - self.extra_cols = 2 + self.add_left_rbl + self.add_right_rbl + self.extra_cols = 2 + len(self.left_rbl) + len(self.right_rbl) - self.create_all_bitline_names() - self.create_all_wordline_names() - self.create_netlist() if not OPTS.netlist_only: self.create_layout() @@ -94,37 +92,45 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array): # Bitcell array self.bitcell_array = factory.create(module_type="bitcell_array", - column_offset=1 + self.add_left_rbl, + column_offset=1 + len(self.left_rbl), cols=self.column_size, rows=self.row_size) self.add_mod(self.bitcell_array) # Replica bitlines self.replica_columns = {} - for bit in range(self.add_left_rbl + self.add_right_rbl): - # Creating left_rbl - if bit < self.add_left_rbl: + + for port in self.all_ports: + if port in self.left_rbl: + # We will always have self.rbl[0] rows of replica wordlines below + # the array. # These go from the top (where the bitcell array starts ) down - replica_bit = self.left_rbl - bit - # Creating right_rbl - else: + replica_bit = self.rbl[0] - port + elif port in self.right_rbl: + + # We will always have self.rbl[0] rows of replica wordlines below + # the array. # These go from the bottom up - replica_bit = self.left_rbl + self.row_size + 1 + bit + replica_bit = self.rbl[0] + self.row_size + 1 + port + else: + continue + # If we have an odd numer on the bottom - column_offset = self.left_rbl + 1 - self.replica_columns[bit] = factory.create(module_type="replica_column", - rows=self.row_size, - rbl=self.rbl, - column_offset=column_offset, - replica_bit=replica_bit) - self.add_mod(self.replica_columns[bit]) + column_offset = self.rbl[0] + 1 + + self.replica_columns[port] = factory.create(module_type="replica_column", + rows=self.row_size, + rbl=self.rbl, + column_offset=column_offset, + replica_bit=replica_bit) + self.add_mod(self.replica_columns[port]) # Dummy row self.dummy_row = factory.create(module_type="dummy_array", cols=self.column_size, rows=1, # dummy column + left replica column - column_offset=1 + self.add_left_rbl, + column_offset=1 + len(self.left_rbl), mirror=0) self.add_mod(self.dummy_row) @@ -140,7 +146,7 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array): cols=self.column_size, rows=1, # dummy column + left replica column(s) - column_offset=1 + self.add_left_rbl, + column_offset=1 + len(self.left_rbl), mirror=0) self.add_mod(self.col_cap) @@ -151,7 +157,7 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array): cols=1, column_offset=0, rows=self.row_size + self.extra_rows, - mirror=(self.left_rbl + 1) % 2) + mirror=(self.rbl[0] + 1) % 2) self.add_mod(self.row_cap_left) self.row_cap_right = factory.create(module_type=row_cap_module_type, @@ -160,9 +166,9 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array): # + left replica column(s) # + bitcell columns # + right replica column(s) - column_offset = 1 + self.add_left_rbl + self.column_size + self.add_right_rbl, + column_offset = 1 + len(self.left_rbl) + self.column_size + len(self.right_rbl), rows=self.row_size + self.extra_rows, - mirror=(self.left_rbl + 1) %2) + mirror=(self.rbl[0] + 1) %2) self.add_mod(self.row_cap_right) def add_pins(self): @@ -186,73 +192,55 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array): self.add_pin("gnd", "GROUND") def add_bitline_pins(self): - # Regular bitline names by port - self.bitline_names = [] - # Replica bitlines by port - self.rbl_bitline_names = [] - - for x in range(self.add_left_rbl + self.add_right_rbl): - self.rbl_bitline_names.append([]) + # The bit is which port the RBL is for + for bit in self.rbls: for port in self.all_ports: - self.rbl_bitline_names[-1].append("rbl_bl_{0}_{1}".format(port, x)) - for port in self.all_ports: - self.rbl_bitline_names[-1].append("rbl_br_{0}_{1}".format(port, x)) - + self.rbl_bitline_names[bit].append("rbl_bl_{0}_{1}".format(port, bit)) + self.rbl_bitline_names[bit].append("rbl_br_{0}_{1}".format(port, bit)) # Make a flat list too self.all_rbl_bitline_names = [x for sl in self.rbl_bitline_names for x in sl] - for port in self.all_ports: - bitline_names = self.bitcell_array.get_bitline_names(port) - self.bitline_names.append(bitline_names) + self.bitline_names = self.bitcell_array.bitline_names # Make a flat list too self.all_bitline_names = [x for sl in zip(*self.bitline_names) for x in sl] - for port in range(self.add_left_rbl): + for port in self.left_rbl: self.add_pin_list(self.rbl_bitline_names[port], "INOUT") self.add_pin_list(self.all_bitline_names, "INOUT") - for port in range(self.add_left_rbl, self.add_left_rbl + self.add_right_rbl): + for port in self.right_rbl: self.add_pin_list(self.rbl_bitline_names[port], "INOUT") def add_wordline_pins(self): - # Regular wordlines by port - self.wordline_names = [] - # Replica wordlines by port - self.rbl_wordline_names = [] # Wordlines to ground self.gnd_wordline_names = [] - self.dummy_row_wordline_names = ["gnd"] * len(self.col_cap.get_wordline_names()) - - for port in range(self.left_rbl + self.right_rbl): - self.rbl_wordline_names.append([]) - for x in self.all_ports: - self.rbl_wordline_names[-1].append("rbl_wl_{0}_{1}".format(x, port)) - if x != port: - self.gnd_wordline_names.append("rbl_wl_{0}_{1}".format(x, port)) + for port in self.all_ports: + for bit in self.all_ports: + self.rbl_wordline_names[port].append("rbl_wl_{0}_{1}".format(port, bit)) + if bit != port: + self.gnd_wordline_names.append("rbl_wl_{0}_{1}".format(port, bit)) self.all_rbl_wordline_names = [x for sl in self.rbl_wordline_names for x in sl] - for port in self.all_ports: - wordline_names = self.bitcell_array.get_wordline_names(port) - self.wordline_names.append(wordline_names) - self.all_wordline_names = [x for sl in zip(*self.wordline_names) for x in sl] + self.wordline_names = self.bitcell_array.wordline_names + self.all_wordline_names = self.bitcell_array.all_wordline_names # All wordlines including dummy and RBL self.replica_array_wordline_names = [] - self.replica_array_wordline_names.extend(self.dummy_row_wordline_names) - for p in range(self.left_rbl): - self.replica_array_wordline_names.extend([x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[p]]) + self.replica_array_wordline_names.extend(["gnd"] * len(self.col_cap.get_wordline_names())) + for bit in range(self.rbl[0]): + self.replica_array_wordline_names.extend([x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[bit]]) self.replica_array_wordline_names.extend(self.all_wordline_names) - for p in range(self.left_rbl, self.left_rbl + self.right_rbl): - self.replica_array_wordline_names.extend([x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[p]]) - self.replica_array_wordline_names.extend(self.dummy_row_wordline_names) + for bit in range(self.rbl[1]): + self.replica_array_wordline_names.extend([x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[self.rbl[0] + bit]]) + self.replica_array_wordline_names.extend(["gnd"] * len(self.col_cap.get_wordline_names())) - for port in range(self.left_rbl): - self.add_pin(self.rbl_wordline_names[port][0], "INPUT") + for port in range(self.rbl[0]): + self.add_pin(self.rbl_wordline_names[port][port], "INPUT") self.add_pin_list(self.all_wordline_names, "INPUT") - for port in range(self.left_rbl, self.left_rbl + self.right_rbl): - self.add_pin(self.rbl_wordline_names[port][1], "INPUT") + for port in range(self.rbl[0], self.rbl[0] + self.rbl[1]): + self.add_pin(self.rbl_wordline_names[port][port], "INPUT") def create_instances(self): """ Create the module instances used in this design """ @@ -269,27 +257,30 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array): # Replica columns self.replica_col_insts = [] - for port in range(self.add_left_rbl + self.add_right_rbl): - self.replica_col_insts.append(self.add_inst(name="replica_col_{}".format(port), - mod=self.replica_columns[port])) - self.connect_inst(self.rbl_bitline_names[port] + self.replica_array_wordline_names + supplies) + for port in self.all_ports: + if port in self.rbls: + self.replica_col_insts.append(self.add_inst(name="replica_col_{}".format(port), + mod=self.replica_columns[port])) + self.connect_inst(self.rbl_bitline_names[port] + self.replica_array_wordline_names + supplies) + else: + self.replica_col_insts.append(None) # Dummy rows under the bitcell array (connected with with the replica cell wl) self.dummy_row_replica_insts = [] # Note, this is the number of left and right even if we aren't adding the columns to this bitcell array! - for port in range(self.left_rbl + self.right_rbl): + for port in self.all_ports: self.dummy_row_replica_insts.append(self.add_inst(name="dummy_row_{}".format(port), - mod=self.dummy_row)) + mod=self.dummy_row)) self.connect_inst([x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[port]] + supplies) # Top/bottom dummy rows or col caps self.dummy_row_insts = [] self.dummy_row_insts.append(self.add_inst(name="dummy_row_bot", - mod=self.col_cap)) - self.connect_inst(self.dummy_row_wordline_names + supplies) + mod=self.col_cap)) + self.connect_inst(["gnd"] * len(self.col_cap.get_wordline_names()) + supplies) self.dummy_row_insts.append(self.add_inst(name="dummy_row_top", mod=self.col_cap)) - self.connect_inst(self.dummy_row_wordline_names + supplies) + self.connect_inst(["gnd"] * len(self.col_cap.get_wordline_names()) + supplies) # Left/right Dummy columns self.dummy_col_insts = [] @@ -318,7 +309,7 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array): # Array was at (0, 0) but move everything so it is at the lower left # We move DOWN the number of left RBL even if we didn't add the column to this bitcell array - self.translate_all(self.bitcell_offset.scale(-1 - self.add_left_rbl, -1 - self.left_rbl)) + self.translate_all(self.bitcell_offset.scale(-1 - len(self.left_rbl), -1 - self.rbl[0])) self.add_layout_pins() @@ -332,47 +323,47 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array): """ Add replica columns on left and right of array """ # Grow from left to right, toward the array - for bit in range(self.add_left_rbl): - offset = self.bitcell_offset.scale(-self.add_left_rbl + bit, -self.left_rbl - 1) - self.replica_col_insts[bit].place(offset) + for bit, port in enumerate(self.left_rbl): + offset = self.bitcell_offset.scale(-len(self.left_rbl) + bit, -self.rbl[0] - 1) + self.replica_col_insts[port].place(offset) # Grow to the right of the bitcell array, array outward - for bit in range(self.add_right_rbl): - offset = self.bitcell_array_inst.lr() + self.bitcell_offset.scale(bit, -self.left_rbl - 1) - self.replica_col_insts[self.add_left_rbl + bit].place(offset) + for bit, port in enumerate(self.right_rbl): + offset = self.bitcell_array_inst.lr() + self.bitcell_offset.scale(bit, -self.rbl[0] - 1) + self.replica_col_insts[port].place(offset) # Replica dummy rows # Add the dummy rows even if we aren't adding the replica column to this bitcell array # These grow up, toward the array - for bit in range(self.left_rbl): - self.dummy_row_replica_insts[bit].place(offset=self.bitcell_offset.scale(0, -self.left_rbl + bit + (-self.left_rbl + bit) % 2), - mirror="MX" if (-self.left_rbl + bit) % 2 else "R0") + for bit in range(self.rbl[0]): + self.dummy_row_replica_insts[bit].place(offset=self.bitcell_offset.scale(0, -self.rbl[0] + bit + (-self.rbl[0] + bit) % 2), + mirror="MX" if (-self.rbl[0] + bit) % 2 else "R0") # These grow up, away from the array - for bit in range(self.right_rbl): - self.dummy_row_replica_insts[self.left_rbl + bit].place(offset=self.bitcell_offset.scale(0, bit + bit % 2) + self.bitcell_array_inst.ul(), - mirror="MX" if bit % 2 else "R0") + for bit in range(self.rbl[1]): + self.dummy_row_replica_insts[self.rbl[0] + bit].place(offset=self.bitcell_offset.scale(0, bit + bit % 2) + self.bitcell_array_inst.ul(), + mirror="MX" if bit % 2 else "R0") def add_end_caps(self): """ Add dummy cells or end caps around the array """ # FIXME: These depend on the array size itself # Far top dummy row (first row above array is NOT flipped) - flip_dummy = self.right_rbl % 2 - dummy_row_offset = self.bitcell_offset.scale(0, self.right_rbl + flip_dummy) + self.bitcell_array_inst.ul() + flip_dummy = self.rbl[1] % 2 + dummy_row_offset = self.bitcell_offset.scale(0, self.rbl[1] + flip_dummy) + self.bitcell_array_inst.ul() self.dummy_row_insts[1].place(offset=dummy_row_offset, mirror="MX" if flip_dummy else "R0") # FIXME: These depend on the array size itself # Far bottom dummy row (first row below array IS flipped) - flip_dummy = (self.left_rbl + 1) % 2 - dummy_row_offset = self.bitcell_offset.scale(0, -self.left_rbl - 1 + flip_dummy) + flip_dummy = (self.rbl[0] + 1) % 2 + dummy_row_offset = self.bitcell_offset.scale(0, -self.rbl[0] - 1 + flip_dummy) self.dummy_row_insts[0].place(offset=dummy_row_offset, mirror="MX" if flip_dummy else "R0") # Far left dummy col # Shifted down by the number of left RBLs even if we aren't adding replica column to this bitcell array - dummy_col_offset = self.bitcell_offset.scale(-self.add_left_rbl - 1, -self.left_rbl - 1) + dummy_col_offset = self.bitcell_offset.scale(-len(self.left_rbl) - 1, -self.rbl[0] - 1) self.dummy_col_insts[0].place(offset=dummy_col_offset) # Far right dummy col # Shifted down by the number of left RBLs even if we aren't adding replica column to this bitcell array - dummy_col_offset = self.bitcell_offset.scale(self.add_right_rbl, -self.left_rbl - 1) + self.bitcell_array_inst.lr() + dummy_col_offset = self.bitcell_offset.scale(len(self.right_rbl), -self.rbl[0] - 1) + self.bitcell_array_inst.lr() self.dummy_col_insts[1].place(offset=dummy_col_offset) def add_layout_pins(self): @@ -412,14 +403,15 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array): height=pin.height()) # Replica bitlines - for (names, inst) in zip(self.rbl_bitline_names, self.replica_col_insts): - for (bl_name, pin_name) in zip(names, self.replica_columns[0].all_bitline_names): - pin = inst.get_pin(pin_name) - self.add_layout_pin(text=bl_name, - layer=pin.layer, - offset=pin.ll().scale(1, 0), - width=pin.width(), - height=self.height) + if len(self.rbls) > 0: + for (names, inst) in zip(self.rbl_bitline_names, self.replica_col_insts): + for (bl_name, pin_name) in zip(names, self.replica_columns[self.rbls[0]].all_bitline_names): + pin = inst.get_pin(pin_name) + self.add_layout_pin(text=bl_name, + layer=pin.layer, + offset=pin.ll().scale(1, 0), + width=pin.width(), + height=self.height) # vdd/gnd are only connected in the perimeter cells # replica column should only have a vdd/gnd in the dummy cell on top/bottom @@ -434,7 +426,8 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array): start_layer=pin.layer) for inst in self.replica_col_insts: - self.copy_layout_pin(inst, pin_name) + if inst: + self.copy_layout_pin(inst, pin_name) def analytical_power(self, corner, load): """Power of Bitcell array and bitline in nW.""" diff --git a/compiler/tests/14_replica_bitcell_array_1rw_1r_test.py b/compiler/tests/14_replica_bitcell_array_1rw_1r_test.py index b57d65a7..65bc7848 100755 --- a/compiler/tests/14_replica_bitcell_array_1rw_1r_test.py +++ b/compiler/tests/14_replica_bitcell_array_1rw_1r_test.py @@ -28,8 +28,7 @@ class replica_bitcell_array_1rw_1r_test(openram_test): a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, - rbl=[1, 1], - add_rbl=[0, 0]) + rbl=[1, 1]) self.local_check(a) debug.info(2, "Testing 4x4 left replica array for cell_1rw_1r") @@ -37,14 +36,16 @@ class replica_bitcell_array_1rw_1r_test(openram_test): cols=4, rows=4, rbl=[1, 1], - add_rbl=[1, 0]) + left_rbl=[0]) self.local_check(a) debug.info(2, "Testing 4x4 array left and right replica for cell_1rw_1r") a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, - rbl=[1, 1]) + rbl=[1, 1], + left_rbl=[0], + right_rbl=[1]) self.local_check(a) @@ -55,7 +56,7 @@ class replica_bitcell_array_1rw_1r_test(openram_test): cols=4, rows=4, rbl=[1, 1], - add_rbl=[0, 1]) + right_rbl=[1]) self.local_check(a) globals.end_openram() diff --git a/compiler/tests/15_local_bitcell_array_1rw_1r_test.py b/compiler/tests/15_local_bitcell_array_1rw_1r_test.py index 778d4b5f..01a5c8ee 100755 --- a/compiler/tests/15_local_bitcell_array_1rw_1r_test.py +++ b/compiler/tests/15_local_bitcell_array_1rw_1r_test.py @@ -28,20 +28,21 @@ class local_bitcell_array_1rw_1r_test(openram_test): globals.setup_bitcell() debug.info(2, "Testing 4x4 local bitcell array for cell_1rw_1r without replica") - a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1], add_rbl=[0, 0]) + a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1]) self.local_check(a) debug.info(2, "Testing 4x4 local bitcell array for cell_1rw_1r with replica column") - a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1], add_rbl=[1, 0]) - self.local_check(a) - - debug.info(2, "Testing 4x4 local bitcell array for cell_1rw_1r with replica column") - a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1], add_rbl=[0, 1]) + a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1], right_rbl=[1]) self.local_check(a) debug.info(2, "Testing 4x4 local bitcell array for cell_1rw_1r with replica column") - a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1], add_rbl=[1, 1]) + a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1], left_rbl=[0]) self.local_check(a) + + debug.info(2, "Testing 4x4 local bitcell array for cell_1rw_1r with replica column") + a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1], left_rbl=[0], right_rbl=[1]) + self.local_check(a) + globals.end_openram() diff --git a/compiler/tests/15_local_bitcell_array_test.py b/compiler/tests/15_local_bitcell_array_test.py index 591b0607..45dae1a4 100755 --- a/compiler/tests/15_local_bitcell_array_test.py +++ b/compiler/tests/15_local_bitcell_array_test.py @@ -23,11 +23,11 @@ class local_bitcell_array_test(openram_test): globals.init_openram(config_file) debug.info(2, "Testing 4x4 local bitcell array for 6t_cell without replica") - a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 0], add_rbl=[0, 0]) + a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 0]) self.local_check(a) debug.info(2, "Testing 4x4 local bitcell array for 6t_cell with replica column") - a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 0], add_rbl=[1, 0]) + a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 0], left_rbl=[0]) self.local_check(a) globals.end_openram()