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https://github.com/VLSIDA/OpenRAM.git
synced 2026-08-29 17:39:02 +02:00
Updates to local and global arrays to make bitline and wordlines consistent.
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mrg
@@ -18,7 +18,6 @@ class global_bitcell_array(bitcell_base_array.bitcell_base_array):
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Creates a global bitcell array.
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Rows is an integer number for all local arrays.
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Cols is a list of the array widths.
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add_left_rbl and add_right_
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"""
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def __init__(self, rows, cols, name=""):
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# The total of all columns will be the number of columns
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@@ -28,8 +27,6 @@ class global_bitcell_array(bitcell_base_array.bitcell_base_array):
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debug.check(len(self.all_ports)<=2, "Only support dual port or less in global bitcell array.")
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self.rbl = [1, 1 if len(self.all_ports)>1 else 0]
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self.add_left_rbl = self.rbl[0]
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self.add_right_rbl = self.rbl[1]
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self.create_netlist()
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if not OPTS.netlist_only:
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@@ -58,19 +55,35 @@ class global_bitcell_array(bitcell_base_array.bitcell_base_array):
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self.local_mods = []
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if len(self.column_sizes) == 1:
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la = factory.create(module_type="local_bitcell_array", rows=self.row_size, cols=self.column_sizes[0], rbl=self.rbl, add_rbl=[self.add_left_rbl, self.add_right_rbl])
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la = factory.create(module_type="local_bitcell_array",
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rows=self.row_size,
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cols=self.column_sizes[0],
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rbl=self.rbl,
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left_rbl=[0],
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right_rbl=[1])
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self.add_mod(la)
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self.local_mods.append(la)
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return
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for i, cols in enumerate(self.column_sizes):
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# Always add the left RBLs to the first subarray and the right RBLs to the last subarray
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if i == 0:
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la = factory.create(module_type="local_bitcell_array", rows=self.row_size, cols=cols, rbl=self.rbl, add_rbl=[self.add_left_rbl, 0])
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elif i == len(self.column_sizes) - 1:
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la = factory.create(module_type="local_bitcell_array", rows=self.row_size, cols=cols, rbl=self.rbl, add_rbl=[0, self.add_right_rbl])
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la = factory.create(module_type="local_bitcell_array",
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rows=self.row_size,
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cols=cols,
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rbl=self.rbl,
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left_rbl=[0])
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elif i == len(self.column_sizes) - 1 and len(self.all_ports) > 1:
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la = factory.create(module_type="local_bitcell_array",
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rows=self.row_size,
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cols=cols,
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rbl=self.rbl,
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right_rbl=[1])
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else:
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la = factory.create(module_type="local_bitcell_array", rows=self.row_size, cols=cols, rbl=self.rbl, add_rbl=[0, 0])
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la = factory.create(module_type="local_bitcell_array",
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rows=self.row_size,
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cols=cols,
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rbl=self.rbl)
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self.add_mod(la)
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self.local_mods.append(la)
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@@ -88,10 +101,8 @@ class global_bitcell_array(bitcell_base_array.bitcell_base_array):
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self.rbl_bitline_names = [[] for x in self.all_ports]
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for port in self.all_ports:
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self.bitline_names[port].append("rbl_bl_{}_0".format(port))
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self.rbl_bitline_names[port].append("rbl_bl_{}_0".format(port))
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for port in self.all_ports:
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self.bitline_names[port].append("rbl_br_{}_0".format(port))
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self.rbl_bitline_names[port].append("rbl_br_{}_0".format(port))
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for col in range(self.column_size):
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@@ -102,10 +113,8 @@ class global_bitcell_array(bitcell_base_array.bitcell_base_array):
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if len(self.all_ports) > 1:
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for port in self.all_ports:
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self.bitline_names[port].append("rbl_bl_{}_1".format(port))
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self.rbl_bitline_names[port].append("rbl_bl_{}_1".format(port))
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for port in self.all_ports:
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self.bitline_names[port].append("rbl_br_{}_1".format(port))
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self.rbl_bitline_names[port].append("rbl_br_{}_1".format(port))
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# Make a flat list too
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@@ -138,8 +147,6 @@ class global_bitcell_array(bitcell_base_array.bitcell_base_array):
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def create_instances(self):
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""" Create the module instances used in this design """
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self.local_insts = []
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for col, mod in zip(self.col_offsets, self.local_mods):
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name = "la_{0}".format(col)
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@@ -193,32 +200,8 @@ class global_bitcell_array(bitcell_base_array.bitcell_base_array):
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def route(self):
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# Route the global wordlines (assumes pins all line up)
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for port in self.all_ports:
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port_inputs = [x for x in self.local_mods[0].get_inputs() if "wl_{}".format(port) in x]
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for i, pin_name in enumerate(port_inputs):
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pins = [x.get_pin(pin_name) for x in self.local_insts]
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y_offset = pins[0].cy()
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if port == 0:
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y_offset -= 1.5 * self.m3_pitch
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else:
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y_offset += 1.5 * self.m3_pitch
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start_offset = vector(pins[0].lx(), y_offset)
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end_offset = vector(pins[-1].rx(), y_offset)
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self.add_layout_pin_segment_center(text=pin_name,
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layer="m3",
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start=start_offset,
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end=end_offset)
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for pin in pins:
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self.add_via_stack_center(from_layer=pin.layer,
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to_layer="m3",
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offset=pin.center())
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end_offset = vector(pin.cx(), y_offset)
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self.add_path("m3", [pin.center(), end_offset])
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pass
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def add_layout_pins(self):
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# Regular bitlines
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@@ -237,10 +220,13 @@ class global_bitcell_array(bitcell_base_array.bitcell_base_array):
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new_name = "{0}_{1}".format(base_name, col + col_value)
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self.copy_layout_pin(inst, pin_name, new_name)
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# Replica wordlines
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self.copy_layout_pin(self.local_insts[0], "rbl_wl_0_0")
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if len(self.all_ports) > 1:
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self.copy_layout_pin(self.local_insts[-1], "rbl_wl_1_1")
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for wl_name in self.local_mods[0].get_inputs():
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left_pin = self.local_insts[0].get_pin(wl_name)
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right_pin = self.local_insts[-1].get_pin(wl_name)
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self.add_layout_pin_segment_center(text=wl_name,
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layer=left_pin.layer,
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start=left_pin.lc(),
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end=right_pin.rc())
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# Replica bitlines
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self.copy_layout_pin(self.local_insts[0], "rbl_bl_0_0")
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@@ -249,10 +235,10 @@ class global_bitcell_array(bitcell_base_array.bitcell_base_array):
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if len(self.all_ports) > 1:
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self.copy_layout_pin(self.local_insts[0], "rbl_bl_1_0")
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self.copy_layout_pin(self.local_insts[0], "rbl_br_1_0")
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self.copy_layout_pin(self.local_insts[-1], "rbl_bl_0_0", "rbl_bl_0_1")
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self.copy_layout_pin(self.local_insts[-1], "rbl_br_0_0", "rbl_br_0_1")
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self.copy_layout_pin(self.local_insts[-1], "rbl_bl_1_0", "rbl_bl_1_1")
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self.copy_layout_pin(self.local_insts[-1], "rbl_br_1_0", "rbl_br_1_1")
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self.copy_layout_pin(self.local_insts[-1], "rbl_bl_0_1")
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self.copy_layout_pin(self.local_insts[-1], "rbl_br_0_1")
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self.copy_layout_pin(self.local_insts[-1], "rbl_bl_1_1")
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self.copy_layout_pin(self.local_insts[-1], "rbl_br_1_1")
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for inst in self.insts:
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self.copy_power_pins(inst, "vdd")
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