merge in dev

compiler/characterizer/simulation.py

@@ -577,7 +577,7 @@ class simulation():
         Gets the signal name associated with the bitlines in the bank.
         """
         # FIXME: change to a solution that does not depend on the technology
-        if OPTS.tech_name == 'sky130':
+        if OPTS.tech_name == "sky130" and len(self.all_ports) == 1:
             cell_mod = factory.create(module_type=OPTS.bitcell, version="opt1")
         else:
             cell_mod = factory.create(module_type=OPTS.bitcell)
@@ -608,5 +608,3 @@ class simulation():
         for i in range(1, len(delays)):
             delay+=delays[i]
         return delay
-
-

compiler/characterizer/stimuli.py

@@ -299,6 +299,8 @@ class stimuli():
 
         self.sf.write("* {} process corner\n".format(self.process))
         for item in self.device_libraries:
+            if OPTS.spice_name:
+                item[0] = item[0].replace("SIMULATOR", OPTS.spice_name.lower())
             if os.path.isfile(item[0]):
                 self.sf.write(".lib \"{0}\" {1}\n".format(item[0], item[1]))
             else:
@@ -307,6 +309,8 @@ class stimuli():
         includes = self.device_models + [circuit]
 
         for item in list(includes):
+            if OPTS.spice_name:
+                item = item.replace("SIMULATOR", OPTS.spice_name.lower())
             self.sf.write(".include \"{0}\"\n".format(item))
 
     def add_comment(self, msg):

compiler/router/router.py

@@ -711,6 +711,27 @@ class router(router_tech):
         p = pin_layout("", [ll, ur], self.get_layer(track[2]))
         return p
 
+    def convert_tracks_to_pin(self, tracks):
+        """
+        Convert a list of grid point into a rectangle shape.
+        Must all be on the same layer.
+        """
+        for t in tracks:
+            debug.check(t[2] == tracks[0][2], "Different layers used.")
+            
+        # For each shape, convert it to a pin
+        pins = [self.convert_track_to_pin(t) for t in tracks]
+        # Now find the bounding box
+        minx = min([p.lx() for p in pins])
+        maxx = max([p.rx() for p in pins])
+        miny = min([p.by() for p in pins])
+        maxy = max([p.uy() for p in pins])
+        ll = vector(minx, miny)
+        ur = vector(maxx, maxy)
+        
+        p = pin_layout("", [ll, ur], self.get_layer(tracks[0][2]))
+        return p
+    
     def convert_track_to_shape_pin(self, track):
         """
         Convert a grid point into a rectangle shape
@@ -1294,8 +1315,25 @@ class router(router_tech):
 
     def get_perimeter_pin(self):
         """ Return the shape of the last routed path that was on the perimeter """
-        for v in self.paths[-1]:
+        lastpath = self.paths[-1]
+        for v in lastpath:
             if self.rg.is_target(v):
+                # Find neighboring grid to make double wide pin
+                neighbor = v + vector3d(0, 1, 0)
+                if neighbor in lastpath:
+                    return self.convert_tracks_to_pin([v, neighbor])
+                neighbor = v + vector3d(0, -1, 0)
+                if neighbor in lastpath:
+                    return self.convert_tracks_to_pin([v, neighbor])
+                neighbor = v + vector3d(1, 0, 0)
+                if neighbor in lastpath:
+                    return self.convert_tracks_to_pin([v, neighbor])
+                neighbor = v + vector3d(-1, 0, 0)
+                if neighbor in lastpath:
+                    return self.convert_tracks_to_pin([v, neighbor])
+
+                # Else if we came from a different layer, we can only add
+                # a signle grid
                 return self.convert_track_to_pin(v)
                 
         return None

compiler/sram/sram_1bank.py

@@ -452,7 +452,6 @@ class sram_1bank(sram_base):
                     y_bottom = 0
                     
                 y_offset = y_bottom - self.data_bus_size[port] + 2 * self.m3_pitch
-                           
                 offset = vector(self.control_logic_insts[port].rx() + self.dff.width,
                                 y_offset)
                 cr = channel_route(netlist=route_map,

compiler/tests/20_sram_1bank_ring_test.py

@@ -0,0 +1,51 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys, os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+
+class sram_1bank_nomux_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+        OPTS.supply_pin_type = "ring"
+        from sram_config import sram_config
+        c = sram_config(word_size=4,
+                        num_words=16,
+                        num_banks=1)
+
+        c.words_per_row=1
+        c.recompute_sizes()
+        debug.info(1, "Layout test for {}rw,{}r,{}w sram "
+                   "with {} bit words, {} words, {} words per "
+                   "row, {} banks".format(OPTS.num_rw_ports,
+                                          OPTS.num_r_ports,
+                                          OPTS.num_w_ports,
+                                          c.word_size,
+                                          c.num_words,
+                                          c.words_per_row,
+                                          c.num_banks))
+        a = factory.create(module_type="sram", sram_config=c)
+        self.local_check(a, final_verification=True)
+
+        globals.end_openram()
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/50_riscv_1rw1r_func_test.py

@@ -16,7 +16,7 @@ from sram_factory import factory
 import debug
 
 
-@unittest.skip("SKIPPING 50_riscv_func_test")
+# @unittest.skip("SKIPPING 50_riscv_func_test")
 class riscv_func_test(openram_test):
 
     def runTest(self):
@@ -24,7 +24,6 @@ class riscv_func_test(openram_test):
         globals.init_openram(config_file)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
-        OPTS.local_array_size = 16
         OPTS.num_rw_ports = 1
         OPTS.num_w_ports = 0
         OPTS.num_r_ports = 1
@@ -38,7 +37,7 @@ class riscv_func_test(openram_test):
         from sram_config import sram_config
         c = sram_config(word_size=32,
                         write_size=8,
-                        num_words=256,
+                        num_words=32,
                         num_banks=1)
         c.words_per_row=1
         c.recompute_sizes()
@@ -49,7 +48,7 @@ class riscv_func_test(openram_test):
                                                                                c.num_banks))
         s = factory.create(module_type="sram", sram_config=c)
         corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
-        f = functional(s.s, corner=corner)
+        f = functional(s.s, corner=corner, cycles=50)
         (fail, error) = f.run()
         self.assertTrue(fail, error)
 

compiler/tests/50_riscv_1rw_func_test.py

@@ -0,0 +1,62 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys, os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+
+# @unittest.skip("SKIPPING 50_riscv_func_test")
+class riscv_func_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+        OPTS.analytical_delay = False
+        OPTS.netlist_only = True
+        OPTS.num_rw_ports = 1
+        OPTS.num_w_ports = 0
+        OPTS.num_r_ports = 0
+        globals.setup_bitcell()
+
+        # This is a hack to reload the characterizer __init__ with the spice version
+        from importlib import reload
+        import characterizer
+        reload(characterizer)
+        from characterizer import functional
+        from sram_config import sram_config
+        c = sram_config(word_size=32,
+                        write_size=8,
+                        num_words=32,
+                        num_banks=1)
+        c.words_per_row=1
+        c.recompute_sizes()
+        debug.info(1, "Functional test RISC-V memory"
+                   "{} bit words, {} words, {} words per row, {} banks".format(c.word_size,
+                                                                               c.num_words,
+                                                                               c.words_per_row,
+                                                                               c.num_banks))
+        s = factory.create(module_type="sram", sram_config=c)
+        corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
+        f = functional(s.s, corner=corner, cycles=50)
+        (fail, error) = f.run()
+        self.assertTrue(fail, error)
+
+        globals.end_openram()
+
+# instantiate a copy of the class to actually run the test
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/verify/magic.py

@@ -251,7 +251,7 @@ def write_lvs_script(cell_name, gds_name, sp_name, final_verification=False, out
     if not output_path:
         output_path = OPTS.openram_temp
 
-    # Copy .magicrc file into the output directory
+    # Copy setup.tcl file into the output directory
     setup_file = os.environ.get('OPENRAM_NETGENRC', None)
     if not setup_file:
         setup_file = OPTS.openram_tech + "tech/setup.tcl"