From 1a2865b9b18dc557a418b4a8a173ac1e9ca8a7d2 Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 14 May 2021 17:07:00 -0700 Subject: [PATCH 01/14] Add Xyce tests --- compiler/tests/21_xyce_delay_test.py | 102 +++++++++++++++++++++++ compiler/tests/21_xyce_setuphold_test.py | 67 +++++++++++++++ 2 files changed, 169 insertions(+) create mode 100755 compiler/tests/21_xyce_delay_test.py create mode 100755 compiler/tests/21_xyce_setuphold_test.py diff --git a/compiler/tests/21_xyce_delay_test.py b/compiler/tests/21_xyce_delay_test.py new file mode 100755 index 00000000..04a81886 --- /dev/null +++ b/compiler/tests/21_xyce_delay_test.py @@ -0,0 +1,102 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2021 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys, os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + + +class timing_sram_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + OPTS.spice_name="xyce" + OPTS.analytical_delay = False + OPTS.netlist_only = True + + # This is a hack to reload the characterizer __init__ with the spice version + from importlib import reload + import characterizer + reload(characterizer) + from characterizer import delay + from sram_config import sram_config + c = sram_config(word_size=4, + num_words=16, + num_banks=1) + c.words_per_row=1 + c.recompute_sizes() + debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank") + s = factory.create(module_type="sram", sram_config=c) + + tempspice = OPTS.openram_temp + "temp.sp" + s.sp_write(tempspice) + + probe_address = "1" * s.s.addr_size + probe_data = s.s.word_size - 1 + debug.info(1, "Probe address {0} probe data bit {1}".format(probe_address, probe_data)) + + corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0]) + d = delay(s.s, tempspice, corner) + import tech + loads = [tech.spice["dff_in_cap"]*4] + slews = [tech.spice["rise_time"]*2] + data, port_data = d.analyze(probe_address, probe_data, slews, loads) + # Combine info about port into all data + data.update(port_data[0]) + + if OPTS.tech_name == "freepdk45": + golden_data = {'delay_hl': [0.24042560000000002], + 'delay_lh': [0.24042560000000002], + 'disabled_read0_power': [0.8981647999999998], + 'disabled_read1_power': [0.9101543999999998], + 'disabled_write0_power': [0.9270382999999998], + 'disabled_write1_power': [0.9482969999999998], + 'leakage_power': 2.9792199999999998, + 'min_period': 0.938, + 'read0_power': [1.1107930999999998], + 'read1_power': [1.1143252999999997], + 'slew_hl': [0.2800772], + 'slew_lh': [0.2800772], + 'write0_power': [1.1667769], + 'write1_power': [1.0986076999999999]} + elif OPTS.tech_name == "scn4m_subm": + golden_data = {'delay_hl': [1.884186], + 'delay_lh': [1.884186], + 'disabled_read0_power': [20.86336], + 'disabled_read1_power': [22.10636], + 'disabled_write0_power': [22.62321], + 'disabled_write1_power': [23.316010000000002], + 'leakage_power': 13.351170000000002, + 'min_period': 7.188, + 'read0_power': [29.90159], + 'read1_power': [30.47858], + 'slew_hl': [2.042723], + 'slew_lh': [2.042723], + 'write0_power': [32.13199], + 'write1_power': [28.46703]} + else: + self.assertTrue(False) # other techs fail + # Check if no too many or too few results + self.assertTrue(len(data.keys())==len(golden_data.keys())) + + self.assertTrue(self.check_golden_data(data,golden_data,0.25)) + + globals.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/21_xyce_setuphold_test.py b/compiler/tests/21_xyce_setuphold_test.py new file mode 100755 index 00000000..f53212f8 --- /dev/null +++ b/compiler/tests/21_xyce_setuphold_test.py @@ -0,0 +1,67 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2021 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys, os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS + + +class timing_setup_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + OPTS.spice_name="Xyce" + OPTS.analytical_delay = False + OPTS.netlist_only = True + + # This is a hack to reload the characterizer __init__ with the spice version + from importlib import reload + import characterizer + reload(characterizer) + from characterizer import setup_hold + import tech + slews = [tech.spice["rise_time"]*2] + + corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0]) + sh = setup_hold(corner) + data = sh.analyze(slews,slews) + if OPTS.tech_name == "freepdk45": + golden_data = {'hold_times_HL': [-0.0158691], + 'hold_times_LH': [-0.0158691], + 'setup_times_HL': [0.026855499999999997], + 'setup_times_LH': [0.032959]} + elif OPTS.tech_name == "scn4m_subm": + golden_data = {'hold_times_HL': [-0.0805664], + 'hold_times_LH': [-0.11718749999999999], + 'setup_times_HL': [0.16357419999999998], + 'setup_times_LH': [0.1757812]} + elif OPTS.tech_name == "sky130": + golden_data = {'hold_times_HL': [-0.05615234], + 'hold_times_LH': [-0.03173828], + 'setup_times_HL': [0.078125], + 'setup_times_LH': [0.1025391]} + else: + self.assertTrue(False) # other techs fail + + # Check if no too many or too few results + self.assertTrue(len(data.keys())==len(golden_data.keys())) + + self.assertTrue(self.check_golden_data(data,golden_data,0.25)) + + globals.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) From 38322dae4e5ddf97d54d97b81cb446e256eeea96 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 18 May 2021 14:58:57 -0700 Subject: [PATCH 02/14] Xyce can be capital or lower case --- compiler/characterizer/__init__.py | 2 +- compiler/characterizer/charutils.py | 2 +- compiler/characterizer/stimuli.py | 6 +++--- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/compiler/characterizer/__init__.py b/compiler/characterizer/__init__.py index d5bcdbc6..a092ac1e 100644 --- a/compiler/characterizer/__init__.py +++ b/compiler/characterizer/__init__.py @@ -34,7 +34,7 @@ if not OPTS.analytical_delay: else: (OPTS.spice_name, OPTS.spice_exe) = get_tool("spice", ["Xyce", "ngspice", "ngspice.exe", "hspice", "xa"]) - if OPTS.spice_name == "Xyce": + if OPTS.spice_name in ["Xyce", "xyce"]: (OPTS.mpi_name, OPTS.mpi_exe) = get_tool("mpi", ["mpirun"]) OPTS.hier_seperator = ":" else: diff --git a/compiler/characterizer/charutils.py b/compiler/characterizer/charutils.py index b25093a0..59ef3177 100644 --- a/compiler/characterizer/charutils.py +++ b/compiler/characterizer/charutils.py @@ -26,7 +26,7 @@ def parse_spice_list(filename, key): full_filename="{0}xa.meas".format(OPTS.openram_temp) elif OPTS.spice_name == "spectre": full_filename = os.path.join(OPTS.openram_temp, "delay_stim.measure") - elif OPTS.spice_name == "Xyce": + elif OPTS.spice_name in ["Xyce", "xyce"]: full_filename = os.path.join(OPTS.openram_temp, "spice_stdout.log") else: # ngspice/hspice using a .lis file diff --git a/compiler/characterizer/stimuli.py b/compiler/characterizer/stimuli.py index f49f636b..55bdfd09 100644 --- a/compiler/characterizer/stimuli.py +++ b/compiler/characterizer/stimuli.py @@ -271,7 +271,7 @@ class stimuli(): self.sf.write(".OPTIONS POST=1 RUNLVL={0} PROBE\n".format(runlvl)) self.sf.write(".OPTIONS PSF=1 \n") self.sf.write(".OPTIONS HIER_DELIM=1 \n") - elif OPTS.spice_name == "Xyce": + elif OPTS.spice_name in ["Xyce", "xyce"]: self.sf.write(".OPTIONS DEVICE TEMP={}\n".format(self.temperature)) self.sf.write(".OPTIONS MEASURE MEASFAIL=1\n") self.sf.write(".TRAN {0}p {1}n\n".format(timestep, end_time)) @@ -318,7 +318,7 @@ class stimuli(): # Adding a commented out supply for simulators where gnd and 0 are not global grounds. self.sf.write("\n*Nodes gnd and 0 are the same global ground node in ngspice/hspice/xa. Otherwise, this source may be needed.\n") - if OPTS.spice_name == "Xyce": + if OPTS.spice_name in ["Xyce", "xyce"]: self.sf.write("V{0} {0} {1} {2}\n".format(self.gnd_name, gnd_node_name, 0.0)) else: self.sf.write("*V{0} {0} {1} {2}\n".format(self.gnd_name, gnd_node_name, 0.0)) @@ -358,7 +358,7 @@ class stimuli(): temp_stim, OPTS.openram_temp) valid_retcode=0 - elif OPTS.spice_name == "Xyce": + elif OPTS.spice_name in ["Xyce", "xyce"]: if OPTS.num_sim_threads > 1 and OPTS.mpi_name: mpi_cmd = "{0} -np {1}".format(OPTS.mpi_exe, OPTS.num_sim_threads) From 1274824793784ee368bf3bab1b6842a0a867e01b Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 21 May 2021 11:27:15 -0700 Subject: [PATCH 03/14] Restrict to direct KLU solver --- compiler/characterizer/stimuli.py | 1 + 1 file changed, 1 insertion(+) diff --git a/compiler/characterizer/stimuli.py b/compiler/characterizer/stimuli.py index 55bdfd09..49fbc97c 100644 --- a/compiler/characterizer/stimuli.py +++ b/compiler/characterizer/stimuli.py @@ -274,6 +274,7 @@ class stimuli(): elif OPTS.spice_name in ["Xyce", "xyce"]: self.sf.write(".OPTIONS DEVICE TEMP={}\n".format(self.temperature)) self.sf.write(".OPTIONS MEASURE MEASFAIL=1\n") + self.sf.write(".OPTIONS LINSOL type=klu\n") self.sf.write(".TRAN {0}p {1}n\n".format(timestep, end_time)) else: debug.error("Unkown spice simulator {}".format(OPTS.spice_name)) From 8964abc2b7201f2750af0ba5f7ff281597ddaf6a Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 9 Jun 2021 16:02:32 -0700 Subject: [PATCH 04/14] Change simulator based on one in use. --- compiler/characterizer/stimuli.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/compiler/characterizer/stimuli.py b/compiler/characterizer/stimuli.py index 80ddf4fc..edbb767a 100644 --- a/compiler/characterizer/stimuli.py +++ b/compiler/characterizer/stimuli.py @@ -299,6 +299,7 @@ class stimuli(): self.sf.write("* {} process corner\n".format(self.process)) for item in self.device_libraries: + item[0] = item[0].replace("SIMULATOR", OPTS.spice_name.lower()) if os.path.isfile(item[0]): self.sf.write(".lib \"{0}\" {1}\n".format(item[0], item[1])) else: @@ -307,6 +308,7 @@ class stimuli(): includes = self.device_models + [circuit] for item in list(includes): + item = item.replace("SIMULATOR", OPTS.spice_name.lower()) self.sf.write(".include \"{0}\"\n".format(item)) def add_comment(self, msg): From 2e23fffaddaaf9f304da35fc66c6772b836ed6cd Mon Sep 17 00:00:00 2001 From: mrg Date: Sun, 13 Jun 2021 14:18:55 -0700 Subject: [PATCH 05/14] Fix comment --- compiler/verify/magic.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler/verify/magic.py b/compiler/verify/magic.py index 454dc176..18ba53fc 100644 --- a/compiler/verify/magic.py +++ b/compiler/verify/magic.py @@ -74,7 +74,7 @@ def write_drc_script(cell_name, gds_name, extract, final_verification, output_pa magic_file = os.environ.get('OPENRAM_MAGICRC', None) if not magic_file: magic_file = OPTS.openram_tech + "tech/.magicrc" - + if os.path.exists(magic_file): shutil.copy(magic_file, output_path + "/.magicrc") else: @@ -251,7 +251,7 @@ def write_lvs_script(cell_name, gds_name, sp_name, final_verification=False, out if not output_path: output_path = OPTS.openram_temp - # Copy .magicrc file into the output directory + # Copy setup.tcl file into the output directory setup_file = os.environ.get('OPENRAM_NETGENRC', None) if not setup_file: setup_file = OPTS.openram_tech + "tech/setup.tcl" From d6a72aed37dd7f879556b2d3367beeefac709756 Mon Sep 17 00:00:00 2001 From: mrg Date: Sun, 13 Jun 2021 15:00:46 -0700 Subject: [PATCH 06/14] Add 2x1 perimter pins to satisfy minimum area rule. --- compiler/router/router.py | 42 +++++++++++++++++++++++++++++++++++++-- 1 file changed, 40 insertions(+), 2 deletions(-) diff --git a/compiler/router/router.py b/compiler/router/router.py index d5bd4738..f82a6128 100644 --- a/compiler/router/router.py +++ b/compiler/router/router.py @@ -711,6 +711,27 @@ class router(router_tech): p = pin_layout("", [ll, ur], self.get_layer(track[2])) return p + def convert_tracks_to_pin(self, tracks): + """ + Convert a list of grid point into a rectangle shape. + Must all be on the same layer. + """ + for t in tracks: + debug.check(t[2] == tracks[0][2], "Different layers used.") + + # For each shape, convert it to a pin + pins = [self.convert_track_to_pin(t) for t in tracks] + # Now find the bounding box + minx = min([p.lx() for p in pins]) + maxx = max([p.rx() for p in pins]) + miny = min([p.by() for p in pins]) + maxy = max([p.uy() for p in pins]) + ll = vector(minx, miny) + ur = vector(maxx, maxy) + + p = pin_layout("", [ll, ur], self.get_layer(tracks[0][2])) + return p + def convert_track_to_shape_pin(self, track): """ Convert a grid point into a rectangle shape @@ -1294,10 +1315,27 @@ class router(router_tech): def get_perimeter_pin(self): """ Return the shape of the last routed path that was on the perimeter """ - for v in self.paths[-1]: + lastpath = self.paths[-1] + for v in lastpath: if self.rg.is_target(v): + # Find neighboring grid to make double wide pin + neighbor = v + vector3d(0, 1, 0) + if neighbor in lastpath: + return self.convert_tracks_to_pin([v, neighbor]) + neighbor = v + vector3d(0, -1, 0) + if neighbor in lastpath: + return self.convert_tracks_to_pin([v, neighbor]) + neighbor = v + vector3d(1, 0, 0) + if neighbor in lastpath: + return self.convert_tracks_to_pin([v, neighbor]) + neighbor = v + vector3d(-1, 0, 0) + if neighbor in lastpath: + return self.convert_tracks_to_pin([v, neighbor]) + + # Else if we came from a different layer, we can only add + # a signle grid return self.convert_track_to_pin(v) - + return None def get_ll_pin(self, pin_name): From 53107a8322b5ba48081ef66de62b7eec752c95ea Mon Sep 17 00:00:00 2001 From: mrg Date: Sun, 13 Jun 2021 15:03:41 -0700 Subject: [PATCH 07/14] Add ring test --- compiler/tests/20_sram_1bank_ring_test.py | 51 +++++++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100755 compiler/tests/20_sram_1bank_ring_test.py diff --git a/compiler/tests/20_sram_1bank_ring_test.py b/compiler/tests/20_sram_1bank_ring_test.py new file mode 100755 index 00000000..e34920c2 --- /dev/null +++ b/compiler/tests/20_sram_1bank_ring_test.py @@ -0,0 +1,51 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2021 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys, os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + + +class sram_1bank_nomux_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + OPTS.supply_pin_type = "ring" + from sram_config import sram_config + c = sram_config(word_size=4, + num_words=16, + num_banks=1) + + c.words_per_row=1 + c.recompute_sizes() + debug.info(1, "Layout test for {}rw,{}r,{}w sram " + "with {} bit words, {} words, {} words per " + "row, {} banks".format(OPTS.num_rw_ports, + OPTS.num_r_ports, + OPTS.num_w_ports, + c.word_size, + c.num_words, + c.words_per_row, + c.num_banks)) + a = factory.create(module_type="sram", sram_config=c) + self.local_check(a, final_verification=True) + + globals.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) From 159d0ed603e07201390efeaeeb9f1ade89bfc261 Mon Sep 17 00:00:00 2001 From: mrg Date: Sun, 13 Jun 2021 15:08:05 -0700 Subject: [PATCH 08/14] Fix s_en spacing problem. --- compiler/sram/sram_1bank.py | 1 - 1 file changed, 1 deletion(-) diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py index 828edfdd..030b0c33 100644 --- a/compiler/sram/sram_1bank.py +++ b/compiler/sram/sram_1bank.py @@ -452,7 +452,6 @@ class sram_1bank(sram_base): y_bottom = 0 y_offset = y_bottom - self.data_bus_size[port] + 2 * self.m3_pitch - offset = vector(self.control_logic_insts[port].rx() + self.dff.width, y_offset) cr = channel_route(netlist=route_map, From 9d7029dadc0566ec0c7f263678a2a6cc78380bd9 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 16 Jun 2021 10:43:04 -0700 Subject: [PATCH 09/14] Only replace simulator if it is defined. --- compiler/characterizer/stimuli.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/compiler/characterizer/stimuli.py b/compiler/characterizer/stimuli.py index edbb767a..dae07048 100644 --- a/compiler/characterizer/stimuli.py +++ b/compiler/characterizer/stimuli.py @@ -299,7 +299,8 @@ class stimuli(): self.sf.write("* {} process corner\n".format(self.process)) for item in self.device_libraries: - item[0] = item[0].replace("SIMULATOR", OPTS.spice_name.lower()) + if OPTS.spice_name: + item[0] = item[0].replace("SIMULATOR", OPTS.spice_name.lower()) if os.path.isfile(item[0]): self.sf.write(".lib \"{0}\" {1}\n".format(item[0], item[1])) else: From 6ac082ce239db4cec7ef5e21c0ec7fd9a701e201 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 16 Jun 2021 10:44:13 -0700 Subject: [PATCH 10/14] Only replace simulator if it is defined. --- compiler/characterizer/stimuli.py | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/compiler/characterizer/stimuli.py b/compiler/characterizer/stimuli.py index edbb767a..384a9f4c 100644 --- a/compiler/characterizer/stimuli.py +++ b/compiler/characterizer/stimuli.py @@ -299,7 +299,8 @@ class stimuli(): self.sf.write("* {} process corner\n".format(self.process)) for item in self.device_libraries: - item[0] = item[0].replace("SIMULATOR", OPTS.spice_name.lower()) + if OPTS.spice_name: + item[0] = item[0].replace("SIMULATOR", OPTS.spice_name.lower()) if os.path.isfile(item[0]): self.sf.write(".lib \"{0}\" {1}\n".format(item[0], item[1])) else: @@ -308,7 +309,8 @@ class stimuli(): includes = self.device_models + [circuit] for item in list(includes): - item = item.replace("SIMULATOR", OPTS.spice_name.lower()) + if OPTS.spice_name: + item = item.replace("SIMULATOR", OPTS.spice_name.lower()) self.sf.write(".include \"{0}\"\n".format(item)) def add_comment(self, msg): From d119a0e7ff52aa8c7675c8f79a73e70ebfe8e7f3 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 16 Jun 2021 18:45:53 -0700 Subject: [PATCH 11/14] Use sky130 bitcell in simulation for BLs --- compiler/characterizer/simulation.py | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/compiler/characterizer/simulation.py b/compiler/characterizer/simulation.py index e985e951..ff2275f6 100644 --- a/compiler/characterizer/simulation.py +++ b/compiler/characterizer/simulation.py @@ -482,7 +482,7 @@ class simulation(): debug.warning("Error occurred while determining SEN name. Can cause faults in simulation.") debug.info(2, "s_en name = {}".format(self.sen_name)) - + column_addr = self.get_column_addr() bl_name_port, br_name_port = self.get_bl_name(self.graph.all_paths, port) port_pos = -1 - len(str(column_addr)) - len(str(port)) @@ -576,7 +576,11 @@ class simulation(): """ Gets the signal name associated with the bitlines in the bank. """ - cell_mod = factory.create(module_type=OPTS.bitcell) + # FIXME: change to a solution that does not depend on the technology + if OPTS.tech_name == 'sky130': + cell_mod = factory.create(module_type=OPTS.bitcell, version="opt1") + else: + cell_mod = factory.create(module_type=OPTS.bitcell) cell_bl = cell_mod.get_bl_name(port) cell_br = cell_mod.get_br_name(port) @@ -588,14 +592,14 @@ class simulation(): for i in range(len(bl_names)): bl_names[i] = bl_names[i].split(OPTS.hier_seperator)[-1] return bl_names[0], bl_names[1] - + def get_empty_measure_data_dict(self): """Make a dict of lists for each type of delay and power measurement to append results to""" measure_names = self.delay_meas_names + self.power_meas_names # Create list of dicts. List lengths is # of ports. Each dict maps the measurement names to lists. measure_data = [{mname: [] for mname in measure_names} for i in self.all_ports] - return measure_data + return measure_data def sum_delays(self, delays): """Adds the delays (delay_data objects) so the correct slew is maintained""" @@ -604,5 +608,3 @@ class simulation(): for i in range(1, len(delays)): delay+=delays[i] return delay - - From c7c319c11f77a0d5e3a929f3b5ae206d02df3b76 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 16 Jun 2021 19:06:12 -0700 Subject: [PATCH 12/14] Use extra bitcell version tag only for single port in sky130 --- compiler/characterizer/simulation.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/characterizer/simulation.py b/compiler/characterizer/simulation.py index ff2275f6..be09ad89 100644 --- a/compiler/characterizer/simulation.py +++ b/compiler/characterizer/simulation.py @@ -577,7 +577,7 @@ class simulation(): Gets the signal name associated with the bitlines in the bank. """ # FIXME: change to a solution that does not depend on the technology - if OPTS.tech_name == 'sky130': + if OPTS.tech_name == "sky130" and self.total_ports == 1: cell_mod = factory.create(module_type=OPTS.bitcell, version="opt1") else: cell_mod = factory.create(module_type=OPTS.bitcell) From b7f1c8e8fc4b8f3328883187ba24c720ae65613f Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 16 Jun 2021 19:07:56 -0700 Subject: [PATCH 13/14] Fix name for detecting single port --- compiler/characterizer/simulation.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/characterizer/simulation.py b/compiler/characterizer/simulation.py index be09ad89..9a8f00f8 100644 --- a/compiler/characterizer/simulation.py +++ b/compiler/characterizer/simulation.py @@ -577,7 +577,7 @@ class simulation(): Gets the signal name associated with the bitlines in the bank. """ # FIXME: change to a solution that does not depend on the technology - if OPTS.tech_name == "sky130" and self.total_ports == 1: + if OPTS.tech_name == "sky130" and len(self.all_ports) == 1: cell_mod = factory.create(module_type=OPTS.bitcell, version="opt1") else: cell_mod = factory.create(module_type=OPTS.bitcell) From afe09025470ddc7e06a7e0e9a72c5339aece9daf Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 16 Jun 2021 19:13:50 -0700 Subject: [PATCH 14/14] Enable small short func tests --- ...nc_test.py => 50_riscv_1rw1r_func_test.py} | 7 +-- compiler/tests/50_riscv_1rw_func_test.py | 62 +++++++++++++++++++ 2 files changed, 65 insertions(+), 4 deletions(-) rename compiler/tests/{50_riscv_func_test.py => 50_riscv_1rw1r_func_test.py} (93%) create mode 100755 compiler/tests/50_riscv_1rw_func_test.py diff --git a/compiler/tests/50_riscv_func_test.py b/compiler/tests/50_riscv_1rw1r_func_test.py similarity index 93% rename from compiler/tests/50_riscv_func_test.py rename to compiler/tests/50_riscv_1rw1r_func_test.py index 5bd55e96..c643621e 100755 --- a/compiler/tests/50_riscv_func_test.py +++ b/compiler/tests/50_riscv_1rw1r_func_test.py @@ -16,7 +16,7 @@ from sram_factory import factory import debug -@unittest.skip("SKIPPING 50_riscv_func_test") +# @unittest.skip("SKIPPING 50_riscv_func_test") class riscv_func_test(openram_test): def runTest(self): @@ -24,7 +24,6 @@ class riscv_func_test(openram_test): globals.init_openram(config_file) OPTS.analytical_delay = False OPTS.netlist_only = True - OPTS.local_array_size = 16 OPTS.num_rw_ports = 1 OPTS.num_w_ports = 0 OPTS.num_r_ports = 1 @@ -38,7 +37,7 @@ class riscv_func_test(openram_test): from sram_config import sram_config c = sram_config(word_size=32, write_size=8, - num_words=256, + num_words=32, num_banks=1) c.words_per_row=1 c.recompute_sizes() @@ -49,7 +48,7 @@ class riscv_func_test(openram_test): c.num_banks)) s = factory.create(module_type="sram", sram_config=c) corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0]) - f = functional(s.s, corner=corner) + f = functional(s.s, corner=corner, cycles=50) (fail, error) = f.run() self.assertTrue(fail, error) diff --git a/compiler/tests/50_riscv_1rw_func_test.py b/compiler/tests/50_riscv_1rw_func_test.py new file mode 100755 index 00000000..00921ec4 --- /dev/null +++ b/compiler/tests/50_riscv_1rw_func_test.py @@ -0,0 +1,62 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2021 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys, os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + + +# @unittest.skip("SKIPPING 50_riscv_func_test") +class riscv_func_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + OPTS.analytical_delay = False + OPTS.netlist_only = True + OPTS.num_rw_ports = 1 + OPTS.num_w_ports = 0 + OPTS.num_r_ports = 0 + globals.setup_bitcell() + + # This is a hack to reload the characterizer __init__ with the spice version + from importlib import reload + import characterizer + reload(characterizer) + from characterizer import functional + from sram_config import sram_config + c = sram_config(word_size=32, + write_size=8, + num_words=32, + num_banks=1) + c.words_per_row=1 + c.recompute_sizes() + debug.info(1, "Functional test RISC-V memory" + "{} bit words, {} words, {} words per row, {} banks".format(c.word_size, + c.num_words, + c.words_per_row, + c.num_banks)) + s = factory.create(module_type="sram", sram_config=c) + corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0]) + f = functional(s.s, corner=corner, cycles=50) + (fail, error) = f.run() + self.assertTrue(fail, error) + + globals.end_openram() + +# instantiate a copy of the class to actually run the test +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner())