mirror of https://github.com/VLSIDA/OpenRAM.git
501 lines
21 KiB
Python
501 lines
21 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2023 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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from math import ceil, log, sqrt
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from openram.base import vector
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from openram.base import design
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from openram import OPTS, debug
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from openram.sram_factory import factory
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from openram.tech import drc, layer
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class rom_base_bank(design):
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"""
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Rom data bank with row and column decoder + control logic
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word size is in bytes
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"""
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def __init__(self, strap_spacing=0, data_file=None, name="", word_size=2):
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super().__init__(name=name)
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self.word_size = word_size * 8
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self.read_binary(word_size=word_size, data_file=data_file, scramble_bits=True, endian="little")
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self.num_outputs = self.rows
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self.num_inputs = ceil(log(self.rows, 2))
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self.col_bits = ceil(log(self.words_per_row, 2))
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self.row_bits = self.num_inputs
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# self.data = [[0, 1, 0, 1], [1, 1, 1, 1], [1, 1, 0, 0], [0, 0, 1, 0]]
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self.strap_spacing = strap_spacing
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self.tap_spacing = 8
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self.interconnect_layer = "m1"
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self.bitline_layer = "m1"
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self.wordline_layer = "m2"
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if "li" in layer:
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self.route_stack = self.m1_stack
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else:
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self.route_stack = self.m2_stack
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self.route_layer = self.route_stack[0]
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self.setup_layout_constants()
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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"""
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Reads a hexadecimal file from a given directory to be used as the data written to the ROM
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endian is either "big" or "little"
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word_size is the number of bytes per word
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sets the row and column size based on the size of binary input, tries to keep array as square as possible,
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"""
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def read_binary(self, data_file, word_size=2, endian="big", scramble_bits=False):
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# Read data as hexidecimal text file
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hex_file = open(data_file, 'r')
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hex_data = hex_file.read()
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# Convert from hex into an int
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data_int = int(hex_data, 16)
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# Then from int into a right aligned, zero padded string
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bin_string = bin(data_int)[2:].zfill(len(hex_data) * 4)
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# Then turn the string into a list of ints
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bin_data = list(bin_string)
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bin_data = [int(x) for x in bin_data]
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# data size in bytes
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data_size = len(bin_data) / 8
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num_words = int(data_size / word_size)
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bytes_per_col = sqrt(num_words)
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self.words_per_row = int(ceil(bytes_per_col /(2*word_size)))
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bits_per_row = self.words_per_row * word_size * 8
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self.cols = bits_per_row
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self.rows = int(num_words / (self.words_per_row))
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chunked_data = []
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for i in range(0, len(bin_data), bits_per_row):
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row_data = bin_data[i:i + bits_per_row]
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if len(row_data) < bits_per_row:
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row_data = [0] * (bits_per_row - len(row_data)) + row_data
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chunked_data.append(row_data)
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# if endian == "big":
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self.data = chunked_data
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if scramble_bits:
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scrambled_chunked = []
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for row_data in chunked_data:
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scambled_data = []
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for bit in range(self.word_size):
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for word in range(self.words_per_row):
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scambled_data.append(row_data[bit + word * self.word_size])
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scrambled_chunked.append(scambled_data)
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self.data = scrambled_chunked
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# self.data.reverse()
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debug.info(1, "Read rom binary: length {0} bytes, {1} words, set number of cols to {2}, rows to {3}, with {4} words per row".format(data_size, num_words, self.cols, self.rows, self.words_per_row))
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def create_netlist(self):
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self.add_modules()
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self.add_pins()
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def create_layout(self):
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self.create_instances()
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self.place_instances()
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self.route_decode_outputs()
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self.route_precharge()
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self.route_clock()
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self.route_array_outputs()
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self.place_top_level_pins()
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self.route_supplies()
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self.route_output_buffers()
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self.height = self.array_inst.height
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self.width = self.array_inst.width
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self.add_boundary()
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def setup_layout_constants(self):
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self.route_layer_width = drc["minwidth_{}".format(self.route_stack[0])]
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self.route_layer_pitch = drc["{0}_to_{0}".format(self.route_stack[0])]
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self.interconnect_layer_width = drc["minwidth_{}".format(self.interconnect_layer)]
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self.interconnect_layer_pitch = drc["{0}_to_{0}".format(self.interconnect_layer)]
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def add_pins(self):
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self.add_pin("clk", "INPUT")
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self.add_pin("CS", "INPUT")
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for i in range(self.row_bits + self.col_bits):
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self.add_pin("addr_{}".format(i), "INPUT")
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out_pins = []
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for j in range(self.word_size):
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out_pins.append("rom_out_{}".format(j))
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self.add_pin_list(out_pins, "OUTPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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def add_modules(self):
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# TODO: provide technology-specific calculation of these parameters
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# in sky130 the address control buffer is composed of 2 size 2 NAND gates,
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# with a beta of 3, each of these gates has gate capacitance of 2 min sized inverters, therefor a load of 4
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addr_control_buffer_effort = 4
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# a single min sized nmos makes up 1/4 of the input capacitance of a min sized inverter
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bitcell_effort = 0.25
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# Takes into account inverter sizing
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wordline_effort = bitcell_effort * 0.5
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# a single min sized pmos plus a single min sized nmos have approximately half the gate capacitance of a min inverter
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# an additional 0.2 accounts for the long wire capacitance and add delay to gaurentee the read timing
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precharge_cell_effort = 0.5 + 0.2
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self.array = factory.create(module_type="rom_base_array",
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cols=self.cols,
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rows=self.rows,
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strap_spacing=self.strap_spacing,
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bitmap=self.data,
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bitline_layer=self.bitline_layer,
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wordline_layer=self.wordline_layer,
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pitch_match=True,
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tap_spacing=self.tap_spacing)
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self.decode_array = factory.create(module_name="rom_row_decode",
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module_type="rom_decoder",
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num_outputs=self.rows,
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strap_spacing=self.strap_spacing,
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route_layer=self.route_layer,
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fanout=(self.cols)*wordline_effort )
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self.column_mux = factory.create(module_type="rom_column_mux_array",
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columns=self.cols,
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word_size=self.word_size,
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tap_spacing=self.strap_spacing,
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bitline_layer=self.interconnect_layer,
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input_layer=self.bitline_layer)
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self.column_decode = factory.create(module_name="rom_column_decode",
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module_type="rom_decoder",
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num_outputs=self.words_per_row,
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strap_spacing=self.strap_spacing,
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route_layer=self.route_layer,
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fanout=2,
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invert_outputs=True )
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self.control_logic = factory.create(module_type="rom_control_logic",
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num_outputs=(self.cols + self.words_per_row * precharge_cell_effort) \
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+ (addr_control_buffer_effort * self.col_bits),
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clk_fanout=(self.row_bits * addr_control_buffer_effort) + (precharge_cell_effort * self.rows),
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height=self.column_decode.height )
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self.bitline_inv = factory.create(module_type="rom_wordline_driver_array",
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module_name="rom_bitline_inverter",
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rows=self.cols,
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fanout=4,
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invert_outputs=True,
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tap_spacing=0,
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flip_io=True)
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self.output_inv = factory.create(module_type="rom_wordline_driver_array",
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module_name="rom_output_buffer",
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rows=self.word_size,
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fanout=4,
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invert_outputs=True)
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def create_instances(self):
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gnd = ["gnd"]
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vdd = ["vdd"]
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prechrg = ["precharge"]
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clk = ["clk_int"]
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bitlines = ["bl_{}".format(bl) for bl in range(self.cols)]
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wordlines = ["wl_{}".format(wl) for wl in range(self.rows)]
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addr_msb = ["addr_{}".format(addr + self.col_bits) for addr in range(self.row_bits)]
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addr_lsb = ["addr_{}".format(addr) for addr in range(self.col_bits)]
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select_lines = ["word_sel_{}".format(word) for word in range(self.words_per_row)]
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bitline_bar = ["bl_b_{}".format(bl) for bl in range(self.cols)]
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pre_buf_outputs = ["rom_out_prebuf_{}".format(bit) for bit in range(self.word_size)]
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outputs = ["rom_out_{}".format(bl) for bl in range(self.word_size)]
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array_pins = bitlines + wordlines + prechrg + vdd + gnd
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row_decode_pins = addr_msb + wordlines + clk + clk + vdd + gnd
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col_decode_pins = addr_lsb + select_lines + prechrg + prechrg + vdd + gnd
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col_mux_pins = bitline_bar + select_lines + pre_buf_outputs + gnd
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bitline_inv_pins = bitlines + bitline_bar + vdd + gnd
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output_buf_pins = pre_buf_outputs + outputs + vdd + gnd
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self.array_inst = self.add_inst(name="rom_bit_array", mod=self.array)
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self.connect_inst(array_pins)
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self.decode_inst = self.add_inst(name="rom_row_decoder", mod=self.decode_array)
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self.connect_inst(row_decode_pins)
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self.control_inst = self.add_inst(name="rom_control", mod=self.control_logic)
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self.connect_inst(["clk", "CS", "precharge", "clk_int", "vdd", "gnd"])
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self.mux_inst = self.add_inst(name="rom_column_mux", mod=self.column_mux)
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self.connect_inst(col_mux_pins)
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self.col_decode_inst = self.add_inst(name="rom_column_decoder", mod=self.column_decode)
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self.connect_inst(col_decode_pins)
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self.bitline_inv_inst = self.add_inst(name="rom_bitline_inverter", mod=self.bitline_inv)
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self.connect_inst(bitline_inv_pins)
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self.output_inv_inst = self.add_inst(name="rom_output_inverter", mod=self.output_inv)
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self.connect_inst(output_buf_pins)
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def place_instances(self):
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self.place_row_decoder()
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self.place_data_array()
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self.place_bitline_inverter()
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self.place_col_mux()
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self.place_col_decoder()
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self.place_control_logic()
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self.place_output_buffer()
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def place_row_decoder(self):
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self.decode_offset = vector(0, self.control_inst.height )
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self.decode_inst.place(offset=self.decode_offset)
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def place_data_array(self):
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# We approximate the correct position for the array
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array_x = self.decode_inst.width + (2) * ( self.route_layer_width + self.route_layer_pitch )
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array_y = self.decode_array.buf_inst.height - self.array.precharge_inst.cy() - self.array.zero_cell.height * 0.5
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self.array_offset = vector(array_x ,array_y)
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self.array_inst.place(offset=self.array_offset)
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# now move array to correct alignment with decoder
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array_align = self.decode_inst.get_pin("wl_0").cy() - self.array_inst.get_pin("wl_0_0").cy()
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self.array_inst.place(offset=(self.array_offset + vector(0, array_align)))
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def place_bitline_inverter(self):
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self.bitline_inv_inst.place(offset=[0,0], rotate=90)
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inv_y_offset = self.array_inst.by() - self.bitline_inv_inst.width - 2 * self.m1_pitch
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inv_x_offset = self.array_inst.get_pin("bl_0_0").cx() - self.bitline_inv_inst.get_pin("out_0").cx()
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self.inv_offset = vector(inv_x_offset, inv_y_offset)
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self.bitline_inv_inst.place(offset=self.inv_offset, rotate=90)
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def place_control_logic(self):
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self.control_offset = vector(self.col_decode_inst.lx() - self.control_inst.width - 3 * self.m1_pitch, self.decode_inst.by() - self.control_logic.height - self.m1_pitch)
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self.control_inst.place(offset=self.control_offset)
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def place_col_decoder(self):
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col_decode_y = self.mux_inst.get_pin("sel_0").cy() - self.col_decode_inst.get_pin("wl_0").cy()
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self.col_decode_offset = vector(self.decode_inst.width - self.col_decode_inst.width, col_decode_y)
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self.col_decode_inst.place(offset=self.col_decode_offset)
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def place_col_mux(self):
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mux_y_offset = self.bitline_inv_inst.by() - self.mux_inst.height - 5 * self.route_layer_pitch
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mux_x_offset = self.bitline_inv_inst.get_pin("out_0").cx() - self.mux_inst.get_pin("bl_0").cx()
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self.mux_offset = vector(mux_x_offset, mux_y_offset)
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self.mux_inst.place(offset=self.mux_offset)
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def place_output_buffer(self):
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output_x = self.col_decode_inst.rx() + self.output_inv_inst.height
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output_y = self.mux_inst.by() - self.word_size * self.m1_pitch
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self.output_inv_offset = vector(output_x, output_y)
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self.output_inv_inst.place(offset=self.output_inv_offset, rotate=270)
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def route_decode_outputs(self):
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# for the row decoder
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route_pins = [self.array_inst.get_pin("wl_0_{}".format(wl)) for wl in range(self.rows)]
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decode_pins = [self.decode_inst.get_pin("wl_{}".format(wl)) for wl in range(self.rows)]
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route_pins.extend(decode_pins)
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self.connect_row_pins(self.interconnect_layer, route_pins, round=True)
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# then for the column decoder
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col_decode_pins = [self.col_decode_inst.get_pin("wl_{}".format(wl)) for wl in range(self.words_per_row)]
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sel_pins = [self.mux_inst.get_pin("sel_{}".format(wl)) for wl in range(self.words_per_row)]
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sel_pins.extend(col_decode_pins)
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self.connect_row_pins(self.wordline_layer, sel_pins, round=True)
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def route_array_inputs(self):
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for wl in range(self.rows):
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array_wl = self.array.wordline_names[0][wl]
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array_wl_pin = self.array_inst.get_pin(array_wl)
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wl_bus_wire = self.wl_bus[self.wl_interconnects[wl]]
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end = array_wl_pin.center()
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start = vector(wl_bus_wire.cx(), end.y)
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self.add_segment_center(self.interconnect_layer, start, end)
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def route_precharge(self):
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prechrg_control = self.control_inst.get_pin("prechrg")
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col_decode_prechrg = self.col_decode_inst.get_pin("precharge_r")
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col_decode_clk = self.col_decode_inst.get_pin("clk")
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array_prechrg = self.array_inst.get_pin("precharge")
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# Route precharge signal to the row decoder
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# end = vector(row_decode_prechrg.cx() - 0.5 * self.interconnect_layer_width, prechrg_control.cy())
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# self.add_segment_center(self.interconnect_layer, prechrg_control.center(), end)
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# start = end + vector(0.5 * self.interconnect_layer_width, 0)
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# self.add_segment_center(self.interconnect_layer, start, row_decode_prechrg.center())
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self.add_via_stack_center(from_layer=self.route_stack[0],
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to_layer=prechrg_control.layer,
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offset=prechrg_control.center())
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# Route precharge to col decoder
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start = prechrg_control.center()
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mid1 = vector(self.control_inst.rx(), prechrg_control.cy())
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mid2 = vector(self.control_inst.rx(), col_decode_prechrg.cy())
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end = col_decode_prechrg.center()
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self.add_path(self.route_stack[0], [start, mid1, mid2, end])
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self.add_via_stack_center(from_layer=self.route_stack[0],
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to_layer=col_decode_prechrg.layer,
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offset=end)
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start = mid1
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mid1 = vector(self.control_inst.rx(), start.y)
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mid2 = vector(mid1.x, col_decode_clk.cy())
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end = col_decode_clk.center()
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self.add_path(self.route_stack[0], [start, mid1, mid2, end])
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# self.add_segment_center(col_decode_prechrg.layer, end, col_decode_prechrg.center())
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# Route precharge to main array
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# end = vector(col_decode_prechrg.cx(), array_prechrg.cy())
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mid = vector(col_decode_prechrg.cx(), array_prechrg.cy() )
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self.add_path(self.route_stack[0], [array_prechrg.center(), mid, col_decode_prechrg.center()])
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def route_clock(self):
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clk_out = self.control_inst.get_pin("clk_out")
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row_decode_clk = self.decode_inst.get_pin("clk")
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self.add_via_stack_center(from_layer=self.route_stack[2],
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to_layer=clk_out.layer,
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offset=clk_out.center())
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# Route clock to row decoder
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mid = vector(self.control_inst.rx() + self.m1_pitch, clk_out.cy())
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addr_control_clk = row_decode_clk.rc() + vector( 2 * self.route_layer_pitch + self.route_layer_width, 0)
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row_decode_prechrg = self.decode_inst.get_pin("precharge")
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self.add_path(self.route_stack[2], [clk_out.center(), mid, addr_control_clk, row_decode_prechrg.center()])
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self.add_via_stack_center(from_layer=self.route_stack[2],
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to_layer=row_decode_clk.layer,
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offset=addr_control_clk)
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self.add_segment_center(row_decode_clk.layer, addr_control_clk, row_decode_clk.rc())
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# Route clock to column decoder
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# end = col_decode_clk.lc() - vector( 2 * self.route_layer_pitch + self.route_layer_width, 0)
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# self.add_path(self.route_stack[2], [clk_out.center(), end])
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# self.add_via_stack_center(from_layer=self.route_stack[2],
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# to_layer=row_decode_clk.layer,
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# offset=end)
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# self.add_segment_center(col_decode_clk.layer, end, col_decode_clk.lc())
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def route_array_outputs(self):
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array_out_pins = [self.array_inst.get_pin("bl_0_{}".format(bl)) for bl in range(self.cols)]
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inv_in_pins = [self.bitline_inv_inst.get_pin("in_{}".format(bl)) for bl in range(self.cols)]
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inv_out_pins = [self.bitline_inv_inst.get_pin("out_{}".format(bl)) for bl in range(self.cols)]
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mux_pins = [self.mux_inst.get_pin("bl_{}".format(bl)) for bl in range(self.cols)]
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self.connect_col_pins(self.interconnect_layer, array_out_pins + inv_in_pins, round=True, directions="nonpref")
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self.connect_col_pins(self.interconnect_layer, inv_out_pins + mux_pins, round=True, directions="nonpref")
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def route_output_buffers(self):
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mux = self.mux_inst
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buf = self.output_inv_inst
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route_nets = [ [mux.get_pin("bl_out_{}".format(bit)), buf.get_pin("in_{}".format(bit))] for bit in range(self.word_size)]
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channel_ll = vector( route_nets[0][0].cx(), route_nets[0][1].cy() + self.m1_pitch * 3)
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self.create_horizontal_channel_route(netlist=route_nets, offset=channel_ll, layer_stack=self.m1_stack)
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def place_top_level_pins(self):
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self.copy_layout_pin(self.control_inst, "CS")
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self.copy_layout_pin(self.control_inst, "clk_in", "clk")
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for i in range(self.word_size):
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self.copy_layout_pin(self.output_inv_inst, "out_{}".format(i), "rom_out_{}".format(i))
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for lsb in range(self.col_bits):
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name = "addr_{}".format(lsb)
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self.copy_layout_pin(self.col_decode_inst, "A{}".format(lsb), name)
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for msb in range(self.col_bits, self.row_bits + self.col_bits):
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name = "addr_{}".format(msb)
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pin_num = msb - self.col_bits
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self.copy_layout_pin(self.decode_inst, "A{}".format(pin_num), name)
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def route_supplies(self):
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for inst in self.insts:
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if not inst.mod.name.__contains__("contact"):
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self.copy_layout_pin(inst, "vdd")
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self.copy_layout_pin(inst, "gnd") |