diff --git a/compiler/modules/capped_bitcell_array.py b/compiler/modules/capped_replica_bitcell_array.py
similarity index 99%
rename from compiler/modules/capped_bitcell_array.py
rename to compiler/modules/capped_replica_bitcell_array.py
index 58fd163a..d9cb256e 100644
--- a/compiler/modules/capped_bitcell_array.py
+++ b/compiler/modules/capped_replica_bitcell_array.py
@@ -14,7 +14,7 @@ from openram import OPTS
 from .bitcell_base_array import bitcell_base_array
 
 
-class capped_bitcell_array(bitcell_base_array):
+class capped_replica_bitcell_array(bitcell_base_array):
     """
     Creates a replica bitcell array then adds the row and column caps to all
     sides of a bitcell array.
diff --git a/compiler/tests/14_capped_bitcell_array_bothrbl_1rw_1r_test.py b/compiler/tests/14_capped_replica_bitcell_array_bothrbl_1rw_1r_test.py
old mode 100644
new mode 100755
similarity index 89%
rename from compiler/tests/14_capped_bitcell_array_bothrbl_1rw_1r_test.py
rename to compiler/tests/14_capped_replica_bitcell_array_bothrbl_1rw_1r_test.py
index 1b860a64..55157f93
--- a/compiler/tests/14_capped_bitcell_array_bothrbl_1rw_1r_test.py
+++ b/compiler/tests/14_capped_replica_bitcell_array_bothrbl_1rw_1r_test.py
@@ -14,7 +14,7 @@ from openram.sram_factory import factory
 from openram import OPTS
 
 
-class capped_bitcell_array_1rw_1r_test(openram_test):
+class capped_replica_bitcell_array_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
@@ -26,7 +26,7 @@ class capped_bitcell_array_1rw_1r_test(openram_test):
         openram.setup_bitcell()
 
         debug.info(2, "Testing 4x4 array left and right replica for dp cell")
-        a = factory.create(module_type="capped_bitcell_array",
+        a = factory.create(module_type="capped_replica_bitcell_array",
                            cols=4,
                            rows=4,
                            rbl=[1, 1],
diff --git a/compiler/tests/14_capped_bitcell_array_leftrbl_1rw_1r_test.py b/compiler/tests/14_capped_replica_bitcell_array_leftrbl_1rw_1r_test.py
old mode 100644
new mode 100755
similarity index 89%
rename from compiler/tests/14_capped_bitcell_array_leftrbl_1rw_1r_test.py
rename to compiler/tests/14_capped_replica_bitcell_array_leftrbl_1rw_1r_test.py
index de0d9177..663f4950
--- a/compiler/tests/14_capped_bitcell_array_leftrbl_1rw_1r_test.py
+++ b/compiler/tests/14_capped_replica_bitcell_array_leftrbl_1rw_1r_test.py
@@ -14,7 +14,7 @@ from openram.sram_factory import factory
 from openram import OPTS
 
 
-class capped_bitcell_array_1rw_1r_test(openram_test):
+class capped_replica_bitcell_array_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
@@ -26,7 +26,7 @@ class capped_bitcell_array_1rw_1r_test(openram_test):
         openram.setup_bitcell()
 
         debug.info(2, "Testing 4x4 left replica array for dp cell")
-        a = factory.create(module_type="capped_bitcell_array",
+        a = factory.create(module_type="capped_replica_bitcell_array",
                            cols=4,
                            rows=4,
                            rbl=[1, 1],
diff --git a/compiler/tests/14_capped_bitcell_array_norbl_1rw_1r_test.py b/compiler/tests/14_capped_replica_bitcell_array_norbl_1rw_1r_test.py
old mode 100644
new mode 100755
similarity index 88%
rename from compiler/tests/14_capped_bitcell_array_norbl_1rw_1r_test.py
rename to compiler/tests/14_capped_replica_bitcell_array_norbl_1rw_1r_test.py
index b2a8d97c..e7d8d4fd
--- a/compiler/tests/14_capped_bitcell_array_norbl_1rw_1r_test.py
+++ b/compiler/tests/14_capped_replica_bitcell_array_norbl_1rw_1r_test.py
@@ -14,7 +14,7 @@ from openram.sram_factory import factory
 from openram import OPTS
 
 
-class capped_bitcell_array_1rw_1r_test(openram_test):
+class capped_replica_bitcell_array_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
@@ -26,7 +26,7 @@ class capped_bitcell_array_1rw_1r_test(openram_test):
         openram.setup_bitcell()
 
         debug.info(2, "Testing 4x4 non-replica array for dp cell")
-        a = factory.create(module_type="capped_bitcell_array",
+        a = factory.create(module_type="capped_replica_bitcell_array",
                            cols=4,
                            rows=4,
                            rbl=[1, 1])