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Add brain-dead router pins to perimeter

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mrg
2020-06-14 15:52:09 -07:00
parent 9930b5f3f6
commit 78be9f367a
3 changed files with 123 additions and 31 deletions
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compiler/modules/control_logic.py
+1 -1
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@@ -1005,7 +1005,7 @@ class control_logic(design.design):
def route_output_to_bus_jogged(self, inst, name):
# Connect this at the bottom of the buffer
out_pos = inst.get_pin("Z").center()
mid1 = vector(out_pos.x, out_pos.y - 0.25 * inst.mod.height)
mid1 = vector(out_pos.x, out_pos.y - 0.4 * inst.mod.height)
mid2 = vector(self.input_bus[name].cx(), mid1.y)
bus_pos = self.input_bus[name].center()
self.add_wire(self.m2_stack[::-1], [out_pos, mid1, mid2, bus_pos])