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Update golden verilog results

This commit is contained in:
mrg 2021-05-05 15:37:27 -07:00
parent f677c8a88d
commit 789a8a1cf0
2 changed files with 18 additions and 0 deletions
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9
compiler/tests/golden/sram_2_16_1_freepdk45.v
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@ -3,6 +3,10 @@
// Word size: 2 // Word size: 2
module sram_2_16_1_freepdk45( module sram_2_16_1_freepdk45(
`ifdef USE_POWER_PINS
vdd,
gnd,
`endif
// Port 0: RW // Port 0: RW
clk0,csb0,web0,addr0,din0,dout0 clk0,csb0,web0,addr0,din0,dout0
); );
@ -15,6 +19,11 @@ module sram_2_16_1_freepdk45(
parameter VERBOSE = 1 ; //Set to 0 to only display warnings parameter VERBOSE = 1 ; //Set to 0 to only display warnings
parameter T_HOLD = 1 ; //Delay to hold dout value after posedge. Value is arbitrary parameter T_HOLD = 1 ; //Delay to hold dout value after posedge. Value is arbitrary
module sram_2_16_1_freepdk45(
`ifdef USE_POWER_PINS
inout vdd;
inout gnd;
`endif
input clk0; // clock input clk0; // clock
input csb0; // active low chip select input csb0; // active low chip select
input web0; // active low write control input web0; // active low write control

9
compiler/tests/golden/sram_2_16_1_scn4m_subm.v
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@ -3,6 +3,10 @@
// Word size: 2 // Word size: 2
module sram_2_16_1_scn4m_subm( module sram_2_16_1_scn4m_subm(
`ifdef USE_POWER_PINS
vdd,
gnd,
`endif
// Port 0: RW // Port 0: RW
clk0,csb0,web0,addr0,din0,dout0 clk0,csb0,web0,addr0,din0,dout0
); );
@ -15,6 +19,11 @@ module sram_2_16_1_scn4m_subm(
parameter VERBOSE = 1 ; //Set to 0 to only display warnings parameter VERBOSE = 1 ; //Set to 0 to only display warnings
parameter T_HOLD = 1 ; //Delay to hold dout value after posedge. Value is arbitrary parameter T_HOLD = 1 ; //Delay to hold dout value after posedge. Value is arbitrary
module sram_2_16_1_scn4m_subm(
`ifdef USE_POWER_PINS
inout vdd;
inout gnd;
`endif
input clk0; // clock input clk0; // clock
input csb0; // active low chip select input csb0; // active low chip select
input web0; // active low write control input web0; // active low write control