From f62016ad9fff6157c3a8e818a8403b95cbfec7f5 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Tue, 3 Mar 2020 12:40:08 +0000 Subject: [PATCH 1/6] revert dff_buf for no body contact --- compiler/modules/dff_buf.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler/modules/dff_buf.py b/compiler/modules/dff_buf.py index 6f06b778..8f581606 100644 --- a/compiler/modules/dff_buf.py +++ b/compiler/modules/dff_buf.py @@ -91,8 +91,8 @@ class dff_buf(design.design): def create_instances(self): self.dff_inst=self.add_inst(name="dff_buf_dff", mod=self.dff) - self.connect_inst(props.dff_buff.buf_ports) - #self.connect_inst(["D", "qint", "clk", "vdd", "gnd"]) + #self.connect_inst(props.dff_buff.buf_ports) + self.connect_inst(["D", "qint", "clk", "vdd", "gnd"]) self.inv1_inst=self.add_inst(name="dff_buf_inv1", mod=self.inv1) From 6e2a5d7a1a29118a1a3d9620118876d5538f3112 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Wed, 1 Apr 2020 04:24:43 -0700 Subject: [PATCH 2/6] set sram output cap in characterizer to be 4x dff input cap --- compiler/characterizer/lib.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py index 6d6c6ce5..d429bcd5 100644 --- a/compiler/characterizer/lib.py +++ b/compiler/characterizer/lib.py @@ -45,7 +45,7 @@ class lib: """ Determine the load/slews if they aren't specified in the config file. """ # These are the parameters to determine the table sizes #self.load_scales = np.array([0.1, 0.25, 0.5, 1, 2, 4, 8]) - self.load_scales = np.array([0.25, 1, 8]) + self.load_scales = np.array([0.25, 1, 4]) #self.load_scales = np.array([0.25, 1]) self.load = tech.spice["dff_in_cap"] self.loads = self.load_scales*self.load From beef9441b72dc8ac045f806bbeb4c2711310be61 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Sun, 5 Apr 2020 02:55:15 -0700 Subject: [PATCH 3/6] fix pin check debug typo --- compiler/base/hierarchy_spice.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/base/hierarchy_spice.py b/compiler/base/hierarchy_spice.py index beb79ded..7adfb4f7 100644 --- a/compiler/base/hierarchy_spice.py +++ b/compiler/base/hierarchy_spice.py @@ -226,7 +226,7 @@ class spice(): subckt_line = list(filter(subckt.search, self.lvs))[0] # parses line into ports and remove subckt lvs_pins = subckt_line.split(" ")[2:] - debug.check(lvs_pins == self.pins, "LVS and spice file pin mismatch.", -1) + debug.check(lvs_pins == self.pins, "LVS and spice file pin mismatch.") def check_net_in_spice(self, net_name): """Checks if a net name exists in the current. Intended to be check nets in hand-made cells.""" From b59c789dec692cee9843277f188486d621d3b35b Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Sun, 5 Apr 2020 03:58:26 -0700 Subject: [PATCH 4/6] remove whitespace --- compiler/modules/dff_buf.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/modules/dff_buf.py b/compiler/modules/dff_buf.py index 8f581606..e42c01c0 100644 --- a/compiler/modules/dff_buf.py +++ b/compiler/modules/dff_buf.py @@ -91,7 +91,7 @@ class dff_buf(design.design): def create_instances(self): self.dff_inst=self.add_inst(name="dff_buf_dff", mod=self.dff) - #self.connect_inst(props.dff_buff.buf_ports) + self.connect_inst(["D", "qint", "clk", "vdd", "gnd"]) self.inv1_inst=self.add_inst(name="dff_buf_inv1", From cd8dc8e20b5431ad58bdb4cf762c8cadd17bd730 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 6 Apr 2020 14:08:38 -0700 Subject: [PATCH 5/6] Output lvs model instead of spice model --- compiler/base/hierarchy_spice.py | 4 ++-- compiler/tests/testutils.py | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/compiler/base/hierarchy_spice.py b/compiler/base/hierarchy_spice.py index beb79ded..8091af63 100644 --- a/compiler/base/hierarchy_spice.py +++ b/compiler/base/hierarchy_spice.py @@ -226,7 +226,7 @@ class spice(): subckt_line = list(filter(subckt.search, self.lvs))[0] # parses line into ports and remove subckt lvs_pins = subckt_line.split(" ")[2:] - debug.check(lvs_pins == self.pins, "LVS and spice file pin mismatch.", -1) + debug.check(lvs_pins == self.pins, "LVS and spice file pin mismatch.") def check_net_in_spice(self, net_name): """Checks if a net name exists in the current. Intended to be check nets in hand-made cells.""" @@ -319,7 +319,7 @@ class spice(): # Including the file path makes the unit test fail for other users. # if os.path.isfile(self.sp_file): # sp.write("\n* {0}\n".format(self.sp_file)) - if lvs_netlist: + if lvs_netlist and hasattr(self, "lvs"): sp.write("\n".join(self.lvs)) else: sp.write("\n".join(self.spice)) diff --git a/compiler/tests/testutils.py b/compiler/tests/testutils.py index 95675c38..c4fd7cac 100644 --- a/compiler/tests/testutils.py +++ b/compiler/tests/testutils.py @@ -39,7 +39,7 @@ class openram_test(unittest.TestCase): tempspice = "{0}{1}.sp".format(OPTS.openram_temp,a.name) tempgds = "{0}{1}.gds".format(OPTS.openram_temp,a.name) - a.sp_write(tempspice) + a.lvs_write(tempspice) # cannot write gds in netlist_only mode if not OPTS.netlist_only: a.gds_write(tempgds) From c8c74e8b695a665a6d258ec1504a04f8e27c9f5d Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 6 Apr 2020 15:20:59 -0700 Subject: [PATCH 6/6] Fix lvs_write in sram class --- compiler/sram/sram.py | 3 +++ compiler/sram/sram_base.py | 9 ++++++--- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/compiler/sram/sram.py b/compiler/sram/sram.py index 0efad5cc..8863c299 100644 --- a/compiler/sram/sram.py +++ b/compiler/sram/sram.py @@ -51,6 +51,9 @@ class sram(): def sp_write(self, name): self.s.sp_write(name) + def lvs_write(self, name): + self.s.lvs_write(name) + def lef_write(self, name): self.s.lef_write(name) diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index 64e3f51b..b9c4c909 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -561,7 +561,7 @@ class sram_base(design, verilog, lef): self.add_via_center(layers=self.m2_stack, offset=out_pos) - def sp_write(self, sp_name): + def sp_write(self, sp_name, lvs_netlist=False): # Write the entire spice of the object to the file ############################################################ # Spice circuit @@ -581,10 +581,13 @@ class sram_base(design, verilog, lef): # sp.write(".global {0} {1}\n".format(spice["vdd_name"], # spice["gnd_name"])) usedMODS = list() - self.sp_write_file(sp, usedMODS) + self.sp_write_file(sp, usedMODS, lvs_netlist=lvs_netlist) del usedMODS sp.close() - + + def lvs_write(self, sp_name): + self.sp_write(sp_name, lvs_netlist=True) + def get_wordline_stage_efforts(self, inp_is_rise=True): """Get the all the stage efforts for each stage in the path from clk_buf to a wordline""" stage_effort_list = []