Clean up config file organization. Improve gdsMill debug output.

2026-09-01 18:48:10 +02:00 · 2019-10-23 10:48:18 -07:00
parent e4b490051d
commit 764d4da1bd
119 changed files with 126 additions and 122 deletions
@@ -19,7 +19,7 @@ import debug
 class pbitcell_array_test(openram_test):

    def runTest(self):
-        globals.init_openram("config_{0}".format(OPTS.tech_name))
+        globals.init_openram("{}/config".format(OPTS.tech_name))

        debug.info(2, "Testing 4x4 array for multiport bitcell, with read ports at the edge of the bit cell")
        OPTS.bitcell = "pbitcell"