diff --git a/compiler/characterizer/setup_hold.py b/compiler/characterizer/setup_hold.py index 8def076d..3739326a 100644 --- a/compiler/characterizer/setup_hold.py +++ b/compiler/characterizer/setup_hold.py @@ -24,6 +24,7 @@ class setup_hold(): # This must match the spice model order self.pins = ["data", "dout", "clk", "vdd", "gnd"] self.model_name = "dff" + print(OPTS.openram_tech) self.model_location = OPTS.openram_tech + "sp_lib/dff.sp" self.period = tech.spice["feasible_period"] diff --git a/compiler/gdsMill/gdsMill/vlsiLayout.py b/compiler/gdsMill/gdsMill/vlsiLayout.py index f4248ebd..671802ae 100644 --- a/compiler/gdsMill/gdsMill/vlsiLayout.py +++ b/compiler/gdsMill/gdsMill/vlsiLayout.py @@ -193,17 +193,21 @@ class VlsiLayout: delegateFunction(startingStructureName, transformPath) #starting with a particular structure, we will recursively traverse the tree #********might have to set the recursion level deeper for big layouts! - if(len(self.structures[startingStructureName].srefs)>0): #does this structure reference any others? - #if so, go through each and call this function again - #if not, return back to the caller (caller can be this function) - for sref in self.structures[startingStructureName].srefs: - #here, we are going to modify the sref coordinates based on the parent objects rotation - self.traverseTheHierarchy(startingStructureName = sref.sName, - delegateFunction = delegateFunction, - transformPath = transformPath, - rotateAngle = sref.rotateAngle, - transFlags = sref.transFlags, - coordinates = sref.coordinates) + try: + if(len(self.structures[startingStructureName].srefs)>0): #does this structure reference any others? + #if so, go through each and call this function again + #if not, return back to the caller (caller can be this function) + for sref in self.structures[startingStructureName].srefs: + #here, we are going to modify the sref coordinates based on the parent objects rotation + self.traverseTheHierarchy(startingStructureName = sref.sName, + delegateFunction = delegateFunction, + transformPath = transformPath, + rotateAngle = sref.rotateAngle, + transFlags = sref.transFlags, + coordinates = sref.coordinates) + except KeyError: + debug.error("Could not find structure {} in GDS file.".format(startingStructureName),-1) + #MUST HANDLE AREFs HERE AS WELL #when we return, drop the last transform from the transformPath del transformPath[-1] diff --git a/compiler/tests/01_library_drc_test.py b/compiler/tests/01_library_drc_test.py index f8da685b..b5578d1b 100755 --- a/compiler/tests/01_library_drc_test.py +++ b/compiler/tests/01_library_drc_test.py @@ -17,7 +17,7 @@ import debug class library_drc_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) import verify (gds_dir, gds_files) = setup_files() diff --git a/compiler/tests/02_library_lvs_test.py b/compiler/tests/02_library_lvs_test.py index ad150a2b..2bb4aa32 100755 --- a/compiler/tests/02_library_lvs_test.py +++ b/compiler/tests/02_library_lvs_test.py @@ -17,7 +17,7 @@ import debug class library_lvs_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) import verify (gds_dir, sp_dir, allnames) = setup_files() diff --git a/compiler/tests/03_contact_test.py b/compiler/tests/03_contact_test.py index 3d7254c3..84e18d80 100755 --- a/compiler/tests/03_contact_test.py +++ b/compiler/tests/03_contact_test.py @@ -18,7 +18,7 @@ import debug class contact_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) for layer_stack in [("metal1", "via1", "metal2"), ("poly", "contact", "metal1")]: stack_name = ":".join(map(str, layer_stack)) diff --git a/compiler/tests/03_path_test.py b/compiler/tests/03_path_test.py index 21001718..a753e609 100755 --- a/compiler/tests/03_path_test.py +++ b/compiler/tests/03_path_test.py @@ -17,7 +17,7 @@ import debug class path_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) import wire_path import tech import design diff --git a/compiler/tests/03_ptx_1finger_nmos_test.py b/compiler/tests/03_ptx_1finger_nmos_test.py index f436d7d0..a174ff54 100755 --- a/compiler/tests/03_ptx_1finger_nmos_test.py +++ b/compiler/tests/03_ptx_1finger_nmos_test.py @@ -18,7 +18,7 @@ import debug class ptx_1finger_nmos_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) import tech debug.info(2, "Checking min size NMOS with 1 finger") diff --git a/compiler/tests/03_ptx_1finger_pmos_test.py b/compiler/tests/03_ptx_1finger_pmos_test.py index ae8078e7..50725055 100755 --- a/compiler/tests/03_ptx_1finger_pmos_test.py +++ b/compiler/tests/03_ptx_1finger_pmos_test.py @@ -18,7 +18,7 @@ import debug class ptx_1finger_pmos_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) import tech debug.info(2, "Checking min size PMOS with 1 finger") diff --git a/compiler/tests/03_ptx_3finger_nmos_test.py b/compiler/tests/03_ptx_3finger_nmos_test.py index c010a948..0f55bd23 100755 --- a/compiler/tests/03_ptx_3finger_nmos_test.py +++ b/compiler/tests/03_ptx_3finger_nmos_test.py @@ -18,7 +18,7 @@ import debug class ptx_3finger_nmos_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) import tech debug.info(2, "Checking three fingers NMOS") diff --git a/compiler/tests/03_ptx_3finger_pmos_test.py b/compiler/tests/03_ptx_3finger_pmos_test.py index 85cca9e2..484ae403 100755 --- a/compiler/tests/03_ptx_3finger_pmos_test.py +++ b/compiler/tests/03_ptx_3finger_pmos_test.py @@ -18,7 +18,7 @@ import debug class ptx_3finger_pmos_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) import tech debug.info(2, "Checking three fingers PMOS") diff --git a/compiler/tests/03_ptx_4finger_nmos_test.py b/compiler/tests/03_ptx_4finger_nmos_test.py index 4a410d51..d4b122c6 100755 --- a/compiler/tests/03_ptx_4finger_nmos_test.py +++ b/compiler/tests/03_ptx_4finger_nmos_test.py @@ -18,7 +18,7 @@ import debug class ptx_4finger_nmos_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) import tech debug.info(2, "Checking three fingers NMOS") diff --git a/compiler/tests/03_ptx_4finger_pmos_test.py b/compiler/tests/03_ptx_4finger_pmos_test.py index 34fbaf9f..f4c5bfe1 100755 --- a/compiler/tests/03_ptx_4finger_pmos_test.py +++ b/compiler/tests/03_ptx_4finger_pmos_test.py @@ -18,7 +18,7 @@ import debug class ptx_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) import tech debug.info(2, "Checking three fingers PMOS") diff --git a/compiler/tests/03_wire_test.py b/compiler/tests/03_wire_test.py index 4ee360ce..9c7f6c3d 100755 --- a/compiler/tests/03_wire_test.py +++ b/compiler/tests/03_wire_test.py @@ -17,7 +17,7 @@ import debug class wire_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) import wire import tech import design diff --git a/compiler/tests/04_dummy_pbitcell_test.py b/compiler/tests/04_dummy_pbitcell_test.py index e8e3cc1c..64964067 100755 --- a/compiler/tests/04_dummy_pbitcell_test.py +++ b/compiler/tests/04_dummy_pbitcell_test.py @@ -18,7 +18,7 @@ import debug class replica_pbitcell_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) import dummy_pbitcell OPTS.bitcell = "pbitcell" diff --git a/compiler/tests/04_pand2_test.py b/compiler/tests/04_pand2_test.py index 42045b43..b2ee471e 100755 --- a/compiler/tests/04_pand2_test.py +++ b/compiler/tests/04_pand2_test.py @@ -18,7 +18,7 @@ import debug class pand2_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) global verify import verify diff --git a/compiler/tests/04_pand3_test.py b/compiler/tests/04_pand3_test.py index 4408f6e8..4a778b20 100755 --- a/compiler/tests/04_pand3_test.py +++ b/compiler/tests/04_pand3_test.py @@ -18,7 +18,7 @@ import debug class pand3_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) global verify import verify diff --git a/compiler/tests/04_pbitcell_test.py b/compiler/tests/04_pbitcell_test.py index 0f14c4c5..16497ca9 100755 --- a/compiler/tests/04_pbitcell_test.py +++ b/compiler/tests/04_pbitcell_test.py @@ -19,7 +19,7 @@ from sram_factory import factory class pbitcell_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) OPTS.num_rw_ports=1 OPTS.num_w_ports=1 diff --git a/compiler/tests/04_pbuf_test.py b/compiler/tests/04_pbuf_test.py index 35db8ccf..e2990beb 100755 --- a/compiler/tests/04_pbuf_test.py +++ b/compiler/tests/04_pbuf_test.py @@ -18,7 +18,7 @@ import debug class pbuf_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) debug.info(2, "Testing inverter/buffer 4x 8x") a = factory.create(module_type="pbuf", size=8) diff --git a/compiler/tests/04_pdriver_test.py b/compiler/tests/04_pdriver_test.py index abaab4a0..bbb790ea 100755 --- a/compiler/tests/04_pdriver_test.py +++ b/compiler/tests/04_pdriver_test.py @@ -18,7 +18,7 @@ import debug class pdriver_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) debug.info(2, "Testing inverter/buffer 4x 8x") # a tests the error message for specifying conflicting conditions diff --git a/compiler/tests/04_pinv_10x_test.py b/compiler/tests/04_pinv_10x_test.py index 2ccce34a..e3c3b6a7 100755 --- a/compiler/tests/04_pinv_10x_test.py +++ b/compiler/tests/04_pinv_10x_test.py @@ -18,7 +18,7 @@ import debug class pinv_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) debug.info(2, "Checking 8x inverter") tx = factory.create(module_type="pinv", size=8) diff --git a/compiler/tests/04_pinv_1x_beta_test.py b/compiler/tests/04_pinv_1x_beta_test.py index 2f96020c..124c31dd 100755 --- a/compiler/tests/04_pinv_1x_beta_test.py +++ b/compiler/tests/04_pinv_1x_beta_test.py @@ -18,7 +18,7 @@ import debug class pinv_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) debug.info(2, "Checking 1x beta=3 size inverter") tx = factory.create(module_type="pinv", size=1, beta=3) diff --git a/compiler/tests/04_pinv_1x_test.py b/compiler/tests/04_pinv_1x_test.py index 9b0f1bc6..cc240f22 100755 --- a/compiler/tests/04_pinv_1x_test.py +++ b/compiler/tests/04_pinv_1x_test.py @@ -18,7 +18,7 @@ import debug class pinv_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) debug.info(2, "Checking 1x size inverter") tx = factory.create(module_type="pinv", size=1) diff --git a/compiler/tests/04_pinv_2x_test.py b/compiler/tests/04_pinv_2x_test.py index d8a7598f..430af7f7 100755 --- a/compiler/tests/04_pinv_2x_test.py +++ b/compiler/tests/04_pinv_2x_test.py @@ -18,7 +18,7 @@ import debug class pinv_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) debug.info(2, "Checking 2x size inverter") tx = factory.create(module_type="pinv", size=2) diff --git a/compiler/tests/04_pinvbuf_test.py b/compiler/tests/04_pinvbuf_test.py index 86af0708..fefb157f 100755 --- a/compiler/tests/04_pinvbuf_test.py +++ b/compiler/tests/04_pinvbuf_test.py @@ -18,7 +18,7 @@ import debug class pinvbuf_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) debug.info(2, "Testing inverter/buffer 4x 8x") a = factory.create(module_type="pinvbuf", size=8) diff --git a/compiler/tests/04_pnand2_test.py b/compiler/tests/04_pnand2_test.py index bc066cfc..1873a38e 100755 --- a/compiler/tests/04_pnand2_test.py +++ b/compiler/tests/04_pnand2_test.py @@ -18,7 +18,7 @@ import debug class pnand2_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) debug.info(2, "Checking 2-input nand gate") tx = factory.create(module_type="pnand2", size=1) diff --git a/compiler/tests/04_pnand3_test.py b/compiler/tests/04_pnand3_test.py index 8bf5098f..c8ea4174 100755 --- a/compiler/tests/04_pnand3_test.py +++ b/compiler/tests/04_pnand3_test.py @@ -18,7 +18,7 @@ import debug class pnand3_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) debug.info(2, "Checking 3-input nand gate") tx = factory.create(module_type="pnand3", size=1) diff --git a/compiler/tests/04_pnor2_test.py b/compiler/tests/04_pnor2_test.py index 0e524506..db93c64f 100755 --- a/compiler/tests/04_pnor2_test.py +++ b/compiler/tests/04_pnor2_test.py @@ -18,7 +18,7 @@ import debug class pnor2_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) debug.info(2, "Checking 2-input nor gate") tx = factory.create(module_type="pnor2", size=1) diff --git a/compiler/tests/04_precharge_test.py b/compiler/tests/04_precharge_test.py index 9b2addd5..a9027ee7 100755 --- a/compiler/tests/04_precharge_test.py +++ b/compiler/tests/04_precharge_test.py @@ -18,7 +18,7 @@ import debug class precharge_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) # check precharge in single port debug.info(2, "Checking precharge for handmade bitcell") diff --git a/compiler/tests/04_replica_pbitcell_test.py b/compiler/tests/04_replica_pbitcell_test.py index 65ce5ecf..1308ac56 100755 --- a/compiler/tests/04_replica_pbitcell_test.py +++ b/compiler/tests/04_replica_pbitcell_test.py @@ -18,7 +18,7 @@ import debug class replica_pbitcell_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) import replica_pbitcell OPTS.bitcell = "pbitcell" diff --git a/compiler/tests/04_single_level_column_mux_test.py b/compiler/tests/04_single_level_column_mux_test.py index 3ecbbe9d..77c8a01c 100755 --- a/compiler/tests/04_single_level_column_mux_test.py +++ b/compiler/tests/04_single_level_column_mux_test.py @@ -20,7 +20,7 @@ import debug class single_level_column_mux_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) # check single level column mux in single port debug.info(2, "Checking column mux") diff --git a/compiler/tests/05_bitcell_1rw_1r_array_test.py b/compiler/tests/05_bitcell_1rw_1r_array_test.py index 972fb8e6..1f96c469 100755 --- a/compiler/tests/05_bitcell_1rw_1r_array_test.py +++ b/compiler/tests/05_bitcell_1rw_1r_array_test.py @@ -21,7 +21,7 @@ class bitcell_1rw_1r_array_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) OPTS.bitcell = "bitcell_1rw_1r" OPTS.replica_bitcell = "replica_bitcell_1rw_1r" diff --git a/compiler/tests/05_bitcell_array_test.py b/compiler/tests/05_bitcell_array_test.py index 6a561019..2c23d40f 100755 --- a/compiler/tests/05_bitcell_array_test.py +++ b/compiler/tests/05_bitcell_array_test.py @@ -20,7 +20,7 @@ import debug class array_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) debug.info(2, "Testing 4x4 array for 6t_cell") a = factory.create(module_type="bitcell_array", cols=4, rows=4) diff --git a/compiler/tests/05_dummy_array_test.py b/compiler/tests/05_dummy_array_test.py index de379a97..40b0436c 100755 --- a/compiler/tests/05_dummy_array_test.py +++ b/compiler/tests/05_dummy_array_test.py @@ -16,7 +16,7 @@ import debug class dummy_row_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) debug.info(2, "Testing dummy row for 6t_cell") a = factory.create(module_type="dummy_array", rows=1, cols=4) diff --git a/compiler/tests/05_pbitcell_array_test.py b/compiler/tests/05_pbitcell_array_test.py index 91bf7522..cc9ee573 100755 --- a/compiler/tests/05_pbitcell_array_test.py +++ b/compiler/tests/05_pbitcell_array_test.py @@ -19,7 +19,7 @@ import debug class pbitcell_array_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) debug.info(2, "Testing 4x4 array for multiport bitcell, with read ports at the edge of the bit cell") OPTS.bitcell = "pbitcell" diff --git a/compiler/tests/05_replica_pbitcell_array_test.py b/compiler/tests/05_replica_pbitcell_array_test.py index 2bc4a0d2..1f66fe11 100755 --- a/compiler/tests/05_replica_pbitcell_array_test.py +++ b/compiler/tests/05_replica_pbitcell_array_test.py @@ -16,7 +16,7 @@ import debug class replica_bitcell_array_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) OPTS.bitcell = "pbitcell" OPTS.replica_bitcell = "replica_pbitcell" diff --git a/compiler/tests/06_hierarchical_decoder_test.py b/compiler/tests/06_hierarchical_decoder_test.py index c349e889..3a407dc1 100755 --- a/compiler/tests/06_hierarchical_decoder_test.py +++ b/compiler/tests/06_hierarchical_decoder_test.py @@ -18,7 +18,7 @@ import debug class hierarchical_decoder_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) # Doesn't require hierarchical decoder # debug.info(1, "Testing 4 row sample for hierarchical_decoder") # a = hierarchical_decoder.hierarchical_decoder(name="hd1, rows=4) diff --git a/compiler/tests/06_hierarchical_predecode2x4_test.py b/compiler/tests/06_hierarchical_predecode2x4_test.py index 0a5363ab..cd730563 100755 --- a/compiler/tests/06_hierarchical_predecode2x4_test.py +++ b/compiler/tests/06_hierarchical_predecode2x4_test.py @@ -18,7 +18,7 @@ import debug class hierarchical_predecode2x4_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) # checking hierarchical precode 2x4 for single port debug.info(1, "Testing sample for hierarchy_predecode2x4") diff --git a/compiler/tests/06_hierarchical_predecode3x8_test.py b/compiler/tests/06_hierarchical_predecode3x8_test.py index b2a8d438..b595cec8 100755 --- a/compiler/tests/06_hierarchical_predecode3x8_test.py +++ b/compiler/tests/06_hierarchical_predecode3x8_test.py @@ -18,7 +18,7 @@ import debug class hierarchical_predecode3x8_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) # checking hierarchical precode 3x8 for single port debug.info(1, "Testing sample for hierarchy_predecode3x8") diff --git a/compiler/tests/07_single_level_column_mux_array_test.py b/compiler/tests/07_single_level_column_mux_array_test.py index c6cd7ed2..cdf2aa47 100755 --- a/compiler/tests/07_single_level_column_mux_array_test.py +++ b/compiler/tests/07_single_level_column_mux_array_test.py @@ -17,7 +17,7 @@ import debug class single_level_column_mux_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) import single_level_column_mux_array # check single level column mux array in single port diff --git a/compiler/tests/08_precharge_array_test.py b/compiler/tests/08_precharge_array_test.py index ee29211b..e03e0308 100755 --- a/compiler/tests/08_precharge_array_test.py +++ b/compiler/tests/08_precharge_array_test.py @@ -18,7 +18,7 @@ import debug class precharge_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) # check precharge array in single port debug.info(2, "Checking 3 column precharge") diff --git a/compiler/tests/08_wordline_driver_test.py b/compiler/tests/08_wordline_driver_test.py index 31415a6c..f39148d9 100755 --- a/compiler/tests/08_wordline_driver_test.py +++ b/compiler/tests/08_wordline_driver_test.py @@ -20,7 +20,7 @@ import debug class wordline_driver_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) # check wordline driver for single port debug.info(2, "Checking driver") diff --git a/compiler/tests/09_sense_amp_array_test.py b/compiler/tests/09_sense_amp_array_test.py index e35ea3c3..52131505 100755 --- a/compiler/tests/09_sense_amp_array_test.py +++ b/compiler/tests/09_sense_amp_array_test.py @@ -18,7 +18,7 @@ import debug class sense_amp_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) # check sense amp array for single port debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2") diff --git a/compiler/tests/10_write_driver_array_test.py b/compiler/tests/10_write_driver_array_test.py index 20dacca6..e2fffd04 100755 --- a/compiler/tests/10_write_driver_array_test.py +++ b/compiler/tests/10_write_driver_array_test.py @@ -18,7 +18,7 @@ import debug class write_driver_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) # check write driver array for single port debug.info(2, "Testing write_driver_array for columns=8, word_size=8") diff --git a/compiler/tests/10_write_driver_array_wmask_test.py b/compiler/tests/10_write_driver_array_wmask_test.py index d09286b5..8acce579 100755 --- a/compiler/tests/10_write_driver_array_wmask_test.py +++ b/compiler/tests/10_write_driver_array_wmask_test.py @@ -20,7 +20,7 @@ import debug class write_driver_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) # check write driver array for single port debug.info(2, "Testing write_driver_array for columns=8, word_size=8, write_size=4") diff --git a/compiler/tests/10_write_mask_and_array_test.py b/compiler/tests/10_write_mask_and_array_test.py index 91155467..5c40b146 100755 --- a/compiler/tests/10_write_mask_and_array_test.py +++ b/compiler/tests/10_write_mask_and_array_test.py @@ -20,7 +20,7 @@ import debug class write_mask_and_array_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) # check write driver array for single port debug.info(2, "Testing write_mask_and_array for columns=8, word_size=8, write_size=4") diff --git a/compiler/tests/11_dff_array_test.py b/compiler/tests/11_dff_array_test.py index b843a6bb..0aed8737 100755 --- a/compiler/tests/11_dff_array_test.py +++ b/compiler/tests/11_dff_array_test.py @@ -18,7 +18,7 @@ import debug class dff_array_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) debug.info(2, "Testing dff_array for 3x3") a = factory.create(module_type="dff_array", rows=3, columns=3) diff --git a/compiler/tests/11_dff_buf_array_test.py b/compiler/tests/11_dff_buf_array_test.py index ec0e7742..ad0ab517 100755 --- a/compiler/tests/11_dff_buf_array_test.py +++ b/compiler/tests/11_dff_buf_array_test.py @@ -18,7 +18,7 @@ import debug class dff_buf_array_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) debug.info(2, "Testing dff_buf_array for 3x3") a = factory.create(module_type="dff_buf_array", rows=3, columns=3) diff --git a/compiler/tests/11_dff_buf_test.py b/compiler/tests/11_dff_buf_test.py index 161deaa2..e8b4a2d9 100755 --- a/compiler/tests/11_dff_buf_test.py +++ b/compiler/tests/11_dff_buf_test.py @@ -18,7 +18,7 @@ import debug class dff_buf_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) debug.info(2, "Testing dff_buf 4x 8x") a = factory.create(module_type="dff_buf", inv1_size=4, inv2_size=8) diff --git a/compiler/tests/12_tri_gate_array_test.py b/compiler/tests/12_tri_gate_array_test.py index 0bd5f60c..c297f399 100755 --- a/compiler/tests/12_tri_gate_array_test.py +++ b/compiler/tests/12_tri_gate_array_test.py @@ -18,7 +18,7 @@ import debug class tri_gate_array_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) debug.info(1, "Testing tri_gate_array for columns=8, word_size=8") a = factory.create(module_type="tri_gate_array", columns=8, word_size=8) diff --git a/compiler/tests/13_delay_chain_test.py b/compiler/tests/13_delay_chain_test.py index 9dc8faeb..2483010b 100755 --- a/compiler/tests/13_delay_chain_test.py +++ b/compiler/tests/13_delay_chain_test.py @@ -18,7 +18,7 @@ import debug class delay_chain_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) debug.info(2, "Testing delay_chain") a = factory.create(module_type="delay_chain", fanout_list=[4, 4, 4, 4]) diff --git a/compiler/tests/14_replica_bitcell_1rw_1r_array_test.py b/compiler/tests/14_replica_bitcell_1rw_1r_array_test.py index bae7edde..f4fb5587 100755 --- a/compiler/tests/14_replica_bitcell_1rw_1r_array_test.py +++ b/compiler/tests/14_replica_bitcell_1rw_1r_array_test.py @@ -16,7 +16,7 @@ import debug class replica_bitcell_array_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) OPTS.bitcell = "bitcell_1rw_1r" OPTS.replica_bitcell = "replica_bitcell_1rw_1r" diff --git a/compiler/tests/14_replica_bitcell_array_test.py b/compiler/tests/14_replica_bitcell_array_test.py index 2b446758..4e4d115b 100755 --- a/compiler/tests/14_replica_bitcell_array_test.py +++ b/compiler/tests/14_replica_bitcell_array_test.py @@ -16,7 +16,7 @@ import debug class replica_bitcell_array_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) debug.info(2, "Testing 4x4 array for 6t_cell") a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, left_rbl=1, right_rbl=0, bitcell_ports=[0]) diff --git a/compiler/tests/14_replica_column_test.py b/compiler/tests/14_replica_column_test.py index c0db4d17..0146695d 100755 --- a/compiler/tests/14_replica_column_test.py +++ b/compiler/tests/14_replica_column_test.py @@ -16,7 +16,7 @@ import debug class replica_column_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) debug.info(2, "Testing replica column for 6t_cell") a = factory.create(module_type="replica_column", rows=4, left_rbl=1, right_rbl=0, replica_bit=1) diff --git a/compiler/tests/16_control_logic_multiport_test.py b/compiler/tests/16_control_logic_multiport_test.py index 66c34d24..7418f2e8 100755 --- a/compiler/tests/16_control_logic_multiport_test.py +++ b/compiler/tests/16_control_logic_multiport_test.py @@ -22,7 +22,7 @@ import debug class control_logic_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) import control_logic import tech diff --git a/compiler/tests/16_control_logic_test.py b/compiler/tests/16_control_logic_test.py index 92d5c94b..7fcbffd8 100755 --- a/compiler/tests/16_control_logic_test.py +++ b/compiler/tests/16_control_logic_test.py @@ -18,7 +18,7 @@ import debug class control_logic_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) import control_logic import tech diff --git a/compiler/tests/18_port_address_test.py b/compiler/tests/18_port_address_test.py index c8db6ec2..7e38c916 100755 --- a/compiler/tests/18_port_address_test.py +++ b/compiler/tests/18_port_address_test.py @@ -16,7 +16,7 @@ import debug class port_address_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) debug.info(1, "Port address 16 rows") a = factory.create("port_address", cols=16, rows=16) diff --git a/compiler/tests/18_port_data_test.py b/compiler/tests/18_port_data_test.py index e5f94329..dcaacb0b 100755 --- a/compiler/tests/18_port_data_test.py +++ b/compiler/tests/18_port_data_test.py @@ -16,7 +16,7 @@ import debug class port_data_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) from sram_config import sram_config c = sram_config(word_size=4, diff --git a/compiler/tests/18_port_data_wmask_test.py b/compiler/tests/18_port_data_wmask_test.py index e9b70337..bfaf4ae3 100755 --- a/compiler/tests/18_port_data_wmask_test.py +++ b/compiler/tests/18_port_data_wmask_test.py @@ -18,7 +18,7 @@ import debug class port_data_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) from sram_config import sram_config c = sram_config(word_size=16, diff --git a/compiler/tests/19_bank_select_test.py b/compiler/tests/19_bank_select_test.py index e2f5a9a8..a4530bf1 100755 --- a/compiler/tests/19_bank_select_test.py +++ b/compiler/tests/19_bank_select_test.py @@ -18,7 +18,7 @@ import debug class bank_select_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) debug.info(1, "No column mux, rw control logic") a = factory.create(module_type="bank_select", port="rw") diff --git a/compiler/tests/19_multi_bank_test.py b/compiler/tests/19_multi_bank_test.py index 1816cd61..d8f64a37 100755 --- a/compiler/tests/19_multi_bank_test.py +++ b/compiler/tests/19_multi_bank_test.py @@ -19,7 +19,7 @@ import debug class multi_bank_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) from sram_config import sram_config c = sram_config(word_size=4, diff --git a/compiler/tests/19_pmulti_bank_test.py b/compiler/tests/19_pmulti_bank_test.py index 749460fa..9a14f741 100755 --- a/compiler/tests/19_pmulti_bank_test.py +++ b/compiler/tests/19_pmulti_bank_test.py @@ -19,7 +19,7 @@ import debug class multi_bank_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) from sram_config import sram_config OPTS.bitcell = "pbitcell" diff --git a/compiler/tests/19_psingle_bank_test.py b/compiler/tests/19_psingle_bank_test.py index 90e886f4..3708940d 100755 --- a/compiler/tests/19_psingle_bank_test.py +++ b/compiler/tests/19_psingle_bank_test.py @@ -19,7 +19,7 @@ import debug class psingle_bank_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) from sram_config import sram_config OPTS.bitcell = "pbitcell" diff --git a/compiler/tests/19_single_bank_1rw_1r_test.py b/compiler/tests/19_single_bank_1rw_1r_test.py index ab5ce041..e4d53de6 100755 --- a/compiler/tests/19_single_bank_1rw_1r_test.py +++ b/compiler/tests/19_single_bank_1rw_1r_test.py @@ -18,7 +18,7 @@ import debug class single_bank_1rw_1r_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) from sram_config import sram_config OPTS.bitcell = "bitcell_1rw_1r" diff --git a/compiler/tests/19_single_bank_1w_1r_test.py b/compiler/tests/19_single_bank_1w_1r_test.py index 12b9f3a0..0d874605 100755 --- a/compiler/tests/19_single_bank_1w_1r_test.py +++ b/compiler/tests/19_single_bank_1w_1r_test.py @@ -18,7 +18,7 @@ import debug class single_bank_1w_1r_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) from sram_config import sram_config OPTS.bitcell = "bitcell_1w_1r" diff --git a/compiler/tests/19_single_bank_test.py b/compiler/tests/19_single_bank_test.py index 1d010db5..ad1d2a52 100755 --- a/compiler/tests/19_single_bank_test.py +++ b/compiler/tests/19_single_bank_test.py @@ -18,7 +18,7 @@ import debug class single_bank_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) from sram_config import sram_config c = sram_config(word_size=4, diff --git a/compiler/tests/19_single_bank_wmask_test.py b/compiler/tests/19_single_bank_wmask_test.py index 439ffeba..644678d5 100755 --- a/compiler/tests/19_single_bank_wmask_test.py +++ b/compiler/tests/19_single_bank_wmask_test.py @@ -18,7 +18,7 @@ import debug class single_bank_wmask_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) from sram_config import sram_config diff --git a/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py b/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py index fdeae56f..c6621219 100755 --- a/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py +++ b/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py @@ -19,7 +19,7 @@ import debug class psram_1bank_2mux_1rw_1w_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) from sram_config import sram_config OPTS.bitcell = "pbitcell" diff --git a/compiler/tests/20_psram_1bank_2mux_1rw_1w_wmask_test.py b/compiler/tests/20_psram_1bank_2mux_1rw_1w_wmask_test.py index 20fbd8e6..705e6d93 100755 --- a/compiler/tests/20_psram_1bank_2mux_1rw_1w_wmask_test.py +++ b/compiler/tests/20_psram_1bank_2mux_1rw_1w_wmask_test.py @@ -21,7 +21,7 @@ import debug class psram_1bank_2mux_1rw_1w_wmask_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) from sram_config import sram_config OPTS.bitcell = "pbitcell" diff --git a/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py b/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py index a5c01d8f..a619c48e 100755 --- a/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py +++ b/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py @@ -19,7 +19,7 @@ import debug class psram_1bank_2mux_1w_1r_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) from sram_config import sram_config OPTS.bitcell = "pbitcell" diff --git a/compiler/tests/20_psram_1bank_2mux_test.py b/compiler/tests/20_psram_1bank_2mux_test.py index 64fa72ca..c932a95a 100755 --- a/compiler/tests/20_psram_1bank_2mux_test.py +++ b/compiler/tests/20_psram_1bank_2mux_test.py @@ -19,7 +19,7 @@ import debug class psram_1bank_2mux_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) from sram_config import sram_config OPTS.bitcell = "pbitcell" OPTS.replica_bitcell="replica_pbitcell" diff --git a/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py b/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py index 7779b794..e012ce30 100755 --- a/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py +++ b/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py @@ -18,7 +18,7 @@ import debug class psram_1bank_4mux_1rw_1r_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) from sram_config import sram_config OPTS.bitcell = "pbitcell" diff --git a/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py index 60192759..b506b87d 100755 --- a/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py +++ b/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py @@ -18,7 +18,7 @@ import debug class sram_1bank_2mux_1rw_1r_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) from sram_config import sram_config OPTS.bitcell = "bitcell_1rw_1r" diff --git a/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py b/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py index 2e1e848f..18c031c9 100755 --- a/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py +++ b/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py @@ -19,7 +19,7 @@ import debug class psram_1bank_2mux_1w_1r_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) from sram_config import sram_config OPTS.bitcell = "bitcell_1w_1r" diff --git a/compiler/tests/20_sram_1bank_2mux_test.py b/compiler/tests/20_sram_1bank_2mux_test.py index 7e5a4f3a..3d43bb04 100755 --- a/compiler/tests/20_sram_1bank_2mux_test.py +++ b/compiler/tests/20_sram_1bank_2mux_test.py @@ -19,7 +19,7 @@ import debug class sram_1bank_2mux_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) from sram_config import sram_config c = sram_config(word_size=4, num_words=32, diff --git a/compiler/tests/20_sram_1bank_2mux_wmask_test.py b/compiler/tests/20_sram_1bank_2mux_wmask_test.py index 65f025a7..55fe2d0b 100755 --- a/compiler/tests/20_sram_1bank_2mux_wmask_test.py +++ b/compiler/tests/20_sram_1bank_2mux_wmask_test.py @@ -21,7 +21,7 @@ import debug class sram_1bank_2mux_wmask_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) from sram_config import sram_config c = sram_config(word_size=8, write_size=4, diff --git a/compiler/tests/20_sram_1bank_32b_1024_wmask_test.py b/compiler/tests/20_sram_1bank_32b_1024_wmask_test.py index a5232267..4df085e0 100755 --- a/compiler/tests/20_sram_1bank_32b_1024_wmask_test.py +++ b/compiler/tests/20_sram_1bank_32b_1024_wmask_test.py @@ -21,7 +21,7 @@ import debug class sram_1bank_32b_1024_wmask_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) from sram_config import sram_config c = sram_config(word_size=32, write_size=8, diff --git a/compiler/tests/20_sram_1bank_4mux_test.py b/compiler/tests/20_sram_1bank_4mux_test.py index 34af86a1..d849135f 100755 --- a/compiler/tests/20_sram_1bank_4mux_test.py +++ b/compiler/tests/20_sram_1bank_4mux_test.py @@ -19,7 +19,7 @@ import debug class sram_1bank_4mux_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) from sram_config import sram_config c = sram_config(word_size=4, num_words=64, diff --git a/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py index 48a42106..bf8ee8f0 100755 --- a/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py +++ b/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py @@ -18,7 +18,7 @@ import debug class sram_1bank_8mux_1rw_1r_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) from sram_config import sram_config OPTS.bitcell = "bitcell_1rw_1r" diff --git a/compiler/tests/20_sram_1bank_8mux_test.py b/compiler/tests/20_sram_1bank_8mux_test.py index c5eaea75..e056732a 100755 --- a/compiler/tests/20_sram_1bank_8mux_test.py +++ b/compiler/tests/20_sram_1bank_8mux_test.py @@ -19,7 +19,7 @@ import debug class sram_1bank_8mux_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) from sram_config import sram_config c = sram_config(word_size=2, num_words=128, diff --git a/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py index f6bccc13..cb7dbd9f 100755 --- a/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py +++ b/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py @@ -18,7 +18,7 @@ import debug class sram_1bank_nomux_1rw_1r_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) from sram_config import sram_config OPTS.bitcell = "bitcell_1rw_1r" diff --git a/compiler/tests/20_sram_1bank_nomux_test.py b/compiler/tests/20_sram_1bank_nomux_test.py index 650d2ac2..b9bc14a4 100755 --- a/compiler/tests/20_sram_1bank_nomux_test.py +++ b/compiler/tests/20_sram_1bank_nomux_test.py @@ -19,7 +19,7 @@ import debug class sram_1bank_nomux_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) from sram_config import sram_config c = sram_config(word_size=4, num_words=16, diff --git a/compiler/tests/20_sram_1bank_nomux_wmask_test.py b/compiler/tests/20_sram_1bank_nomux_wmask_test.py index e0292e95..26d75d82 100755 --- a/compiler/tests/20_sram_1bank_nomux_wmask_test.py +++ b/compiler/tests/20_sram_1bank_nomux_wmask_test.py @@ -21,7 +21,7 @@ import debug class sram_1bank_nomux_wmask_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) from sram_config import sram_config c = sram_config(word_size=8, write_size=4, diff --git a/compiler/tests/20_sram_2bank_test.py b/compiler/tests/20_sram_2bank_test.py index c5d9d3d0..61b909ec 100755 --- a/compiler/tests/20_sram_2bank_test.py +++ b/compiler/tests/20_sram_2bank_test.py @@ -19,7 +19,7 @@ import debug class sram_2bank_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) from sram_config import sram_config c = sram_config(word_size=16, num_words=32, diff --git a/compiler/tests/21_hspice_delay_test.py b/compiler/tests/21_hspice_delay_test.py index ebb424aa..a1ad05a7 100755 --- a/compiler/tests/21_hspice_delay_test.py +++ b/compiler/tests/21_hspice_delay_test.py @@ -18,7 +18,7 @@ import debug class timing_sram_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) OPTS.spice_name="hspice" OPTS.analytical_delay = False OPTS.netlist_only = True diff --git a/compiler/tests/21_hspice_setuphold_test.py b/compiler/tests/21_hspice_setuphold_test.py index 83bd5509..c309b10a 100755 --- a/compiler/tests/21_hspice_setuphold_test.py +++ b/compiler/tests/21_hspice_setuphold_test.py @@ -18,7 +18,7 @@ import debug class timing_setup_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) OPTS.spice_name="hspice" OPTS.analytical_delay = False OPTS.netlist_only = True diff --git a/compiler/tests/21_model_delay_test.py b/compiler/tests/21_model_delay_test.py index a4de4c2a..1b611808 100755 --- a/compiler/tests/21_model_delay_test.py +++ b/compiler/tests/21_model_delay_test.py @@ -20,7 +20,7 @@ class model_delay_test(openram_test): """ Compare the accuracy of the analytical model with a spice simulation. """ def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) OPTS.analytical_delay = False OPTS.netlist_only = True diff --git a/compiler/tests/21_ngspice_delay_test.py b/compiler/tests/21_ngspice_delay_test.py index a5eb67fa..63ad6022 100755 --- a/compiler/tests/21_ngspice_delay_test.py +++ b/compiler/tests/21_ngspice_delay_test.py @@ -18,7 +18,7 @@ import debug class timing_sram_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) OPTS.spice_name="ngspice" OPTS.analytical_delay = False OPTS.netlist_only = True diff --git a/compiler/tests/21_ngspice_setuphold_test.py b/compiler/tests/21_ngspice_setuphold_test.py index 0d160943..c0db881a 100755 --- a/compiler/tests/21_ngspice_setuphold_test.py +++ b/compiler/tests/21_ngspice_setuphold_test.py @@ -18,7 +18,7 @@ import debug class timing_setup_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) OPTS.spice_name="ngspice" OPTS.analytical_delay = False OPTS.netlist_only = True diff --git a/compiler/tests/22_psram_1bank_2mux_func_test.py b/compiler/tests/22_psram_1bank_2mux_func_test.py index f986c3e7..63d65993 100755 --- a/compiler/tests/22_psram_1bank_2mux_func_test.py +++ b/compiler/tests/22_psram_1bank_2mux_func_test.py @@ -18,7 +18,7 @@ import debug class psram_1bank_2mux_func_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False diff --git a/compiler/tests/22_psram_1bank_4mux_func_test.py b/compiler/tests/22_psram_1bank_4mux_func_test.py index c5fd8945..d688d4a0 100755 --- a/compiler/tests/22_psram_1bank_4mux_func_test.py +++ b/compiler/tests/22_psram_1bank_4mux_func_test.py @@ -19,7 +19,7 @@ import debug class psram_1bank_4mux_func_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False diff --git a/compiler/tests/22_psram_1bank_8mux_func_test.py b/compiler/tests/22_psram_1bank_8mux_func_test.py index acb168c0..6938732c 100755 --- a/compiler/tests/22_psram_1bank_8mux_func_test.py +++ b/compiler/tests/22_psram_1bank_8mux_func_test.py @@ -19,7 +19,7 @@ import debug class psram_1bank_8mux_func_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False diff --git a/compiler/tests/22_psram_1bank_nomux_func_test.py b/compiler/tests/22_psram_1bank_nomux_func_test.py index a2a2b41c..a1d1051c 100755 --- a/compiler/tests/22_psram_1bank_nomux_func_test.py +++ b/compiler/tests/22_psram_1bank_nomux_func_test.py @@ -19,7 +19,7 @@ import debug class psram_1bank_nomux_func_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False diff --git a/compiler/tests/22_sram_1bank_2mux_func_test.py b/compiler/tests/22_sram_1bank_2mux_func_test.py index 2037169e..048ee372 100755 --- a/compiler/tests/22_sram_1bank_2mux_func_test.py +++ b/compiler/tests/22_sram_1bank_2mux_func_test.py @@ -19,7 +19,7 @@ import debug class sram_1bank_2mux_func_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False diff --git a/compiler/tests/22_sram_1bank_4mux_func_test.py b/compiler/tests/22_sram_1bank_4mux_func_test.py index 178f955b..c8bd2657 100755 --- a/compiler/tests/22_sram_1bank_4mux_func_test.py +++ b/compiler/tests/22_sram_1bank_4mux_func_test.py @@ -19,7 +19,7 @@ import debug class sram_1bank_4mux_func_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False diff --git a/compiler/tests/22_sram_1bank_8mux_func_test.py b/compiler/tests/22_sram_1bank_8mux_func_test.py index d531163a..b8d7fc07 100755 --- a/compiler/tests/22_sram_1bank_8mux_func_test.py +++ b/compiler/tests/22_sram_1bank_8mux_func_test.py @@ -19,7 +19,7 @@ import debug class sram_1bank_8mux_func_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False diff --git a/compiler/tests/22_sram_1bank_nomux_func_test.py b/compiler/tests/22_sram_1bank_nomux_func_test.py index eb6d2412..7133fc71 100755 --- a/compiler/tests/22_sram_1bank_nomux_func_test.py +++ b/compiler/tests/22_sram_1bank_nomux_func_test.py @@ -19,7 +19,7 @@ import debug class sram_1bank_nomux_func_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) OPTS.analytical_delay = False OPTS.netlist_only = True diff --git a/compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py b/compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py index 169e34d0..a24610a2 100755 --- a/compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py +++ b/compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py @@ -19,7 +19,7 @@ import debug class psram_1bank_nomux_func_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False diff --git a/compiler/tests/22_sram_wmask_1w_1r_func_test.py b/compiler/tests/22_sram_wmask_1w_1r_func_test.py index 2ee79750..afd8310a 100755 --- a/compiler/tests/22_sram_wmask_1w_1r_func_test.py +++ b/compiler/tests/22_sram_wmask_1w_1r_func_test.py @@ -21,7 +21,7 @@ import debug class sram_wmask_1w_1r_func_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False diff --git a/compiler/tests/22_sram_wmask_func_test.py b/compiler/tests/22_sram_wmask_func_test.py index c390f030..8b3fa90d 100755 --- a/compiler/tests/22_sram_wmask_func_test.py +++ b/compiler/tests/22_sram_wmask_func_test.py @@ -19,7 +19,7 @@ import debug class sram_wmask_func_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False diff --git a/compiler/tests/23_lib_sram_model_corners_test.py b/compiler/tests/23_lib_sram_model_corners_test.py index 5840c05d..5020a5c9 100755 --- a/compiler/tests/23_lib_sram_model_corners_test.py +++ b/compiler/tests/23_lib_sram_model_corners_test.py @@ -18,7 +18,7 @@ import debug class lib_model_corners_lib_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) OPTS.netlist_only = True from characterizer import lib diff --git a/compiler/tests/23_lib_sram_model_test.py b/compiler/tests/23_lib_sram_model_test.py index 75e73f71..399daf7e 100755 --- a/compiler/tests/23_lib_sram_model_test.py +++ b/compiler/tests/23_lib_sram_model_test.py @@ -18,7 +18,7 @@ import debug class lib_sram_model_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) OPTS.netlist_only = True from characterizer import lib diff --git a/compiler/tests/23_lib_sram_prune_test.py b/compiler/tests/23_lib_sram_prune_test.py index 1fc5a66b..cd10fb10 100755 --- a/compiler/tests/23_lib_sram_prune_test.py +++ b/compiler/tests/23_lib_sram_prune_test.py @@ -18,7 +18,7 @@ import debug class lib_sram_prune_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) OPTS.analytical_delay = False OPTS.trim_netlist = True diff --git a/compiler/tests/23_lib_sram_test.py b/compiler/tests/23_lib_sram_test.py index 0ababf32..5a60e9ad 100755 --- a/compiler/tests/23_lib_sram_test.py +++ b/compiler/tests/23_lib_sram_test.py @@ -17,7 +17,7 @@ import debug class lib_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) OPTS.analytical_delay = False OPTS.trim_netlist = False diff --git a/compiler/tests/24_lef_sram_test.py b/compiler/tests/24_lef_sram_test.py index 5f7fdc60..3390c2e2 100755 --- a/compiler/tests/24_lef_sram_test.py +++ b/compiler/tests/24_lef_sram_test.py @@ -18,7 +18,7 @@ import debug class lef_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) from sram import sram from sram_config import sram_config diff --git a/compiler/tests/25_verilog_sram_test.py b/compiler/tests/25_verilog_sram_test.py index da6a2682..e44f081a 100755 --- a/compiler/tests/25_verilog_sram_test.py +++ b/compiler/tests/25_verilog_sram_test.py @@ -17,7 +17,7 @@ import debug class verilog_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) from sram import sram from sram_config import sram_config diff --git a/compiler/tests/26_hspice_pex_pinv_test.py b/compiler/tests/26_hspice_pex_pinv_test.py index f0cccba3..7d99120c 100755 --- a/compiler/tests/26_hspice_pex_pinv_test.py +++ b/compiler/tests/26_hspice_pex_pinv_test.py @@ -20,7 +20,7 @@ import debug class hspice_pex_pinv_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) import pinv # load the hspice diff --git a/compiler/tests/26_ngspice_pex_pinv_test.py b/compiler/tests/26_ngspice_pex_pinv_test.py index 2eb95948..96cc72aa 100755 --- a/compiler/tests/26_ngspice_pex_pinv_test.py +++ b/compiler/tests/26_ngspice_pex_pinv_test.py @@ -19,7 +19,7 @@ import debug class ngspice_pex_pinv_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) import pinv # load the ngspice diff --git a/compiler/tests/26_pex_test.py b/compiler/tests/26_pex_test.py index 78409249..3fd63117 100755 --- a/compiler/tests/26_pex_test.py +++ b/compiler/tests/26_pex_test.py @@ -19,7 +19,7 @@ import debug class sram_func_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + globals.init_openram("{}/config".format(OPTS.tech_name)) OPTS.use_pex = True diff --git a/compiler/tests/30_openram_back_end_test.py b/compiler/tests/30_openram_back_end_test.py index de1bec05..16ffbbef 100755 --- a/compiler/tests/30_openram_back_end_test.py +++ b/compiler/tests/30_openram_back_end_test.py @@ -20,7 +20,7 @@ class openram_back_end_test(openram_test): def runTest(self): OPENRAM_HOME = os.path.abspath(os.environ.get("OPENRAM_HOME")) - globals.init_openram("{0}/tests/config_{1}".format(OPENRAM_HOME,OPTS.tech_name)) + globals.init_openram("{0}/tests/{1}/config".format(OPENRAM_HOME,OPTS.tech_name)) debug.info(1, "Testing top-level back-end openram.py with 2-bit, 16 word SRAM.") out_file = "testsram" @@ -51,7 +51,7 @@ class openram_back_end_test(openram_test): exe_name = "{0}/openram.py ".format(OPENRAM_HOME) else: exe_name = "coverage run -p {0}/openram.py ".format(OPENRAM_HOME) - config_name = "{0}config_{1}_back_end.py".format(OPENRAM_HOME + "/tests/",OPTS.tech_name) + config_name = "{0}/tests/{1}/config_back_end.py".format(OPENRAM_HOME,OPTS.tech_name) cmd = "{0} -n -o {1} -p {2} {3} {4} 2>&1 > {5}/output.log".format(exe_name, out_file, out_path, diff --git a/compiler/tests/30_openram_front_end_test.py b/compiler/tests/30_openram_front_end_test.py index dbe7fcb9..58b70574 100755 --- a/compiler/tests/30_openram_front_end_test.py +++ b/compiler/tests/30_openram_front_end_test.py @@ -16,12 +16,11 @@ from sram_factory import factory import debug import getpass -#@unittest.skip("SKIPPING 30_openram_front_end_test") class openram_front_end_test(openram_test): def runTest(self): OPENRAM_HOME = os.path.abspath(os.environ.get("OPENRAM_HOME")) - globals.init_openram("{0}/tests/config_{1}".format(OPENRAM_HOME,OPTS.tech_name)) + globals.init_openram("{0}/tests/{1}/config".format(OPENRAM_HOME,OPTS.tech_name)) debug.info(1, "Testing top-level front-end openram.py with 2-bit, 16 word SRAM.") out_file = "testsram" @@ -52,7 +51,7 @@ class openram_front_end_test(openram_test): exe_name = "{0}/openram.py ".format(OPENRAM_HOME) else: exe_name = "coverage run -p {0}/openram.py ".format(OPENRAM_HOME) - config_name = "{0}config_{1}_front_end.py".format(OPENRAM_HOME + "/tests/",OPTS.tech_name) + config_name = "{0}/tests/{1}/config_front_end.py".format(OPENRAM_HOME,OPTS.tech_name) cmd = "{0} -n -o {1} -p {2} {3} {4} 2>&1 > {5}/output.log".format(exe_name, out_file, out_path, diff --git a/compiler/tests/config_freepdk45.py b/compiler/tests/freepdk45/config.py similarity index 100% rename from compiler/tests/config_freepdk45.py rename to compiler/tests/freepdk45/config.py diff --git a/compiler/tests/config_freepdk45_back_end.py b/compiler/tests/freepdk45/config_back_end.py similarity index 100% rename from compiler/tests/config_freepdk45_back_end.py rename to compiler/tests/freepdk45/config_back_end.py diff --git a/compiler/tests/config_freepdk45_front_end.py b/compiler/tests/freepdk45/config_front_end.py similarity index 100% rename from compiler/tests/config_freepdk45_front_end.py rename to compiler/tests/freepdk45/config_front_end.py diff --git a/compiler/tests/config_scn3me_subm.py b/compiler/tests/scn3me_subm/config.py similarity index 100% rename from compiler/tests/config_scn3me_subm.py rename to compiler/tests/scn3me_subm/config.py diff --git a/compiler/tests/config_scn3me_subm_back_end.py b/compiler/tests/scn3me_subm/config_back_end.py similarity index 100% rename from compiler/tests/config_scn3me_subm_back_end.py rename to compiler/tests/scn3me_subm/config_back_end.py diff --git a/compiler/tests/config_scn3me_subm_front_end.py b/compiler/tests/scn3me_subm/config_front_end.py similarity index 100% rename from compiler/tests/config_scn3me_subm_front_end.py rename to compiler/tests/scn3me_subm/config_front_end.py diff --git a/compiler/tests/config_scn4m_subm.py b/compiler/tests/scn4m_subm/config.py similarity index 100% rename from compiler/tests/config_scn4m_subm.py rename to compiler/tests/scn4m_subm/config.py diff --git a/compiler/tests/config_scn4m_subm_back_end.py b/compiler/tests/scn4m_subm/config_back_end.py similarity index 100% rename from compiler/tests/config_scn4m_subm_back_end.py rename to compiler/tests/scn4m_subm/config_back_end.py diff --git a/compiler/tests/config_scn4m_subm_front_end.py b/compiler/tests/scn4m_subm/config_front_end.py similarity index 100% rename from compiler/tests/config_scn4m_subm_front_end.py rename to compiler/tests/scn4m_subm/config_front_end.py