From 74cab877820369a0762ed5003409ecd737e354a8 Mon Sep 17 00:00:00 2001 From: FriedrichWu Date: Sat, 21 Dec 2024 18:57:06 +0100 Subject: [PATCH] add tech fix --- technology/sky130/tech/tech.py | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/technology/sky130/tech/tech.py b/technology/sky130/tech/tech.py index 0df22cb7..b52a35b3 100755 --- a/technology/sky130/tech/tech.py +++ b/technology/sky130/tech/tech.py @@ -502,7 +502,8 @@ drc["pwell_to_nwell"] = 0 drc.add_layer("nwell", width=0.840, spacing=1.270) - +# nwell.6 Minimum enclosure of nwell hole by deep nwell outside UHVI +drc["minclosure_nwell_by_dnwell"] = 1.030 # poly.1a Minimum width of poly # poly.2 Minimum spacing of poly AND active drc.add_layer("poly", @@ -662,7 +663,8 @@ drc.add_enclosure("m3", drc.add_layer("via3", width=0.200, spacing=0.200) - +# via3.12 Minimum spacing of via3 to via2 (cu) +drc["via3_to_via2"] = 0.180 # m4.1 Minimum width of metal4 # m4.2 Minimum spacing of metal4 # m4.7 Minimum area of metal4 @@ -748,6 +750,7 @@ spice["bitcell_leakage"] = 1 # Leakage power of a single bitcell in nW spice["inv_leakage"] = 1 # Leakage power of inverter in nW spice["nand2_leakage"] = 1 # Leakage power of 2-input nand in nW spice["nand3_leakage"] = 1 # Leakage power of 3-input nand in nW +spice["nand4_leakage"] = 1 # Leakage power of 4-input nand in nW spice["nor2_leakage"] = 1 # Leakage power of 2-input nor in nW spice["dff_leakage"] = 1 # Leakage power of flop in nW