Added a graph exclusion clear for the mux to prevent previous graph creations causing bugs.

compiler/modules/bank.py

@@ -1110,3 +1110,9 @@ class bank(design.design):
         Excludes all columns muxes unrelated to the target bit being simulated.
         """
         self.port_data[port].graph_exclude_column_mux(column_include_num)
+
+    def graph_clear_column_mux(self, port):
+        """
+        Clear mux exclusions to allow different bit tests.
+        """
+        self.port_data[port].graph_clear_column_mux()

compiler/modules/column_mux_array.py

@@ -236,10 +236,6 @@ class column_mux_array(design.design):
         Excludes all columns muxes unrelated to the target bit being simulated.
         Each mux in mux_inst corresponds to respective column in bitcell array.
         """
-        #stop = 34
         for i in range(len(self.mux_inst)):
             if i != column_include_num:
                 self.graph_inst_exclude.add(self.mux_inst[i])
-                debug.info(0, "Excluded mux {}".format(i))
-            #if i == stop:
-             #   break

compiler/modules/port_data.py

@@ -862,4 +862,11 @@ class port_data(design.design):
         Excludes all columns muxes unrelated to the target bit being simulated.
         """
         if self.column_mux_array:
-            self.column_mux_array.graph_exclude_columns(column_include_num)
+            self.column_mux_array.graph_exclude_columns(column_include_num)
+            
+    def graph_clear_column_mux(self):
+        """
+        Clear mux exclusions to allow different bit tests.
+        """
+        if self.column_mux_array:
+            self.column_mux_array.init_graph_params()