From 74b55ea83ba39e9001955372d38e01f8d9b2a482 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Mon, 14 Jun 2021 14:39:54 -0700 Subject: [PATCH] Added a graph exclusion clear for the mux to prevent previous graph creations causing bugs. --- compiler/characterizer/delay.py | 2 +- compiler/characterizer/simulation.py | 3 +-- compiler/modules/bank.py | 6 ++++++ compiler/modules/column_mux_array.py | 4 ---- compiler/modules/port_data.py | 9 ++++++++- compiler/sram/sram_base.py | 5 +++++ 6 files changed, 21 insertions(+), 8 deletions(-) diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index fb5174c6..27d72195 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -246,7 +246,7 @@ class delay(simulation): bl_and_port = self.bl_name.format(port) # bl_name contains a '{}' for the port # Isolate the s_en and bitline paths debug.info(1, "self.bl_name = {0}".format(self.bl_name)) - debug.info(1, "self.graph.all_paths = {0}".format(self.graph.all_paths)) + debug.info(2, "self.graph.all_paths = {0}".format(self.graph.all_paths)) sen_paths = [path for path in self.graph.all_paths if sen_and_port in path] bl_paths = [path for path in self.graph.all_paths if bl_and_port in path] debug.check(len(sen_paths)==1, 'Found {0} paths which contain the s_en net.'.format(len(sen_paths))) diff --git a/compiler/characterizer/simulation.py b/compiler/characterizer/simulation.py index acc3139d..6c357c99 100644 --- a/compiler/characterizer/simulation.py +++ b/compiler/characterizer/simulation.py @@ -534,9 +534,9 @@ class simulation(): self.sram.graph_exclude_bits(self.wordline_row, self.bitline_column) port=0 #FIXME, port_data requires a port specification, assuming single port for now if self.words_per_row > 1: + self.sram.graph_clear_column_mux(port) self.sram.graph_exclude_column_mux(self.bitline_column, port) - debug.info(0, "self.bitline_column={}".format(self.bitline_column)) # Generate new graph every analysis as edges might change depending on test bit self.graph = graph_util.timing_graph() self.sram_instance_name = "X{}".format(self.sram.name) @@ -558,7 +558,6 @@ class simulation(): """ net_found = False for path in paths: - debug.info(0, "path={}".format(path)) aliases = self.sram.find_aliases(self.sram_instance_name, self.pins, path, internal_net, mod, exclusion_set) if net_found and len(aliases) >= 1: debug.error('Found multiple paths with {} net.'.format(internal_net), 1) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index ffff10ff..d6fb3121 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -1110,3 +1110,9 @@ class bank(design.design): Excludes all columns muxes unrelated to the target bit being simulated. """ self.port_data[port].graph_exclude_column_mux(column_include_num) + + def graph_clear_column_mux(self, port): + """ + Clear mux exclusions to allow different bit tests. + """ + self.port_data[port].graph_clear_column_mux() diff --git a/compiler/modules/column_mux_array.py b/compiler/modules/column_mux_array.py index 11502142..544b37e1 100644 --- a/compiler/modules/column_mux_array.py +++ b/compiler/modules/column_mux_array.py @@ -236,10 +236,6 @@ class column_mux_array(design.design): Excludes all columns muxes unrelated to the target bit being simulated. Each mux in mux_inst corresponds to respective column in bitcell array. """ - #stop = 34 for i in range(len(self.mux_inst)): if i != column_include_num: self.graph_inst_exclude.add(self.mux_inst[i]) - debug.info(0, "Excluded mux {}".format(i)) - #if i == stop: - # break \ No newline at end of file diff --git a/compiler/modules/port_data.py b/compiler/modules/port_data.py index b2490655..6c73647e 100644 --- a/compiler/modules/port_data.py +++ b/compiler/modules/port_data.py @@ -862,4 +862,11 @@ class port_data(design.design): Excludes all columns muxes unrelated to the target bit being simulated. """ if self.column_mux_array: - self.column_mux_array.graph_exclude_columns(column_include_num) \ No newline at end of file + self.column_mux_array.graph_exclude_columns(column_include_num) + + def graph_clear_column_mux(self): + """ + Clear mux exclusions to allow different bit tests. + """ + if self.column_mux_array: + self.column_mux_array.init_graph_params() \ No newline at end of file diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index b396c745..3a2747cb 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -780,3 +780,8 @@ class sram_base(design, verilog, lef): """ self.bank.graph_exclude_column_mux(column_include_num, port) + def graph_clear_column_mux(self, port): + """ + Clear mux exclusions to allow different bit tests. + """ + self.bank.graph_clear_column_mux(port)