diff --git a/compiler/modules/dummy_bitcell_1port.py b/compiler/modules/dummy_bitcell_1port.py
index b7893326..1556b80c 100644
--- a/compiler/modules/dummy_bitcell_1port.py
+++ b/compiler/modules/dummy_bitcell_1port.py
@@ -21,3 +21,6 @@ class dummy_bitcell_1port(bitcell_base):
         super().__init__(name, prop=props.bitcell_1port)
         debug.info(2, "Create dummy bitcell")
 
+    def build_graph(self, graph, inst_name, port_nets):
+        """ Adds edges based on inputs/outputs. Overrides base class function. """
+        pass
diff --git a/compiler/modules/dummy_bitcell_2port.py b/compiler/modules/dummy_bitcell_2port.py
index 5da53743..af868062 100644
--- a/compiler/modules/dummy_bitcell_2port.py
+++ b/compiler/modules/dummy_bitcell_2port.py
@@ -21,3 +21,6 @@ class dummy_bitcell_2port(bitcell_base):
         super().__init__(name, prop=props.bitcell_2port)
         debug.info(2, "Create dummy bitcell 2 port object")
 
+    def build_graph(self, graph, inst_name, port_nets):
+        """ Adds edges based on inputs/outputs. Overrides base class function. """
+        pass