mirror of https://github.com/VLSIDA/OpenRAM.git
add top level pins for sim
This commit is contained in:
Jacob Walker
parent
81bf2d7ae7
commit
736bd51fe1
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@ -266,7 +266,7 @@ class rom_base_array(bitcell_base_array):
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self.cell_pos[row, col] = vector(cell_x, cell_y)
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self.cell_inst[row, col].place(self.cell_pos[row, col])
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cell_x += self.zero_cell.width
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self.add_label("debug", "li", self.cell_pos[row, col])
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# self.add_label("debug", "li", self.cell_pos[row, col])
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self.strap_pos[row, self.column_size] = vector(cell_x, cell_y)
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@ -326,7 +326,7 @@ class rom_base_array(bitcell_base_array):
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def place_precharge(self):
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self.precharge_offset = vector(0, - self.precharge_inst.height - self.zero_cell.nmos.end_to_contact - 2 * drc["nwell_enclose_active"])
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self.precharge_offset = vector(0, - self.precharge_inst.height - self.zero_cell.nmos.end_to_contact - 2 * drc["nwell_enclose_active"] - 3 * self.m1_pitch)
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self.precharge_inst.place(offset=self.precharge_offset)
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@ -2,7 +2,7 @@
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from math import ceil, log, sqrt
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from openram.base import vector
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from openram.base import design
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from openram import OPTS
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from openram import OPTS, debug
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from openram.sram_factory import factory
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from openram.tech import drc, layer
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@ -14,8 +14,8 @@ class rom_base_bank(design):
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word size is in bytes
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"""
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def __init__(self, strap_spacing=0, data_file=None, name="", word_size=2) -> None:
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def __init__(self, strap_spacing=0, data_file=None, name="", word_size=2):
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super().__init__(name=name)
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self.word_size = word_size * 8
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self.read_binary(word_size=word_size, data_file=data_file)
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@ -31,7 +31,7 @@ class rom_base_bank(design):
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self.bitline_layer = "m1"
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self.wordline_layer = "m2"
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super().__init__(name=name)
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if "li" in layer:
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self.route_stack = self.m1_stack
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else:
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@ -39,6 +39,7 @@ class rom_base_bank(design):
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self.route_layer = self.route_stack[0]
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self.setup_layout_constants()
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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"""
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Reads a hexadecimal file from a given directory to be used as the data written to the ROM
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@ -48,10 +49,17 @@ class rom_base_bank(design):
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"""
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def read_binary(self, data_file, word_size=2, endian="big"):
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# Read data as hexidecimal text file
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hex_file = open(data_file, 'r')
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hex_data = hex_file.read()
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bin_data = list("{0:08b}".format(int(hex_data, 16)))
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# Convert from hex into an int
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data_int = int(hex_data, 16)
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# Then from int into a right aligned, zero padded string
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bin_string = bin(data_int)[2:].zfill(len(hex_data) * 4)
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# Then turn the string into a list of ints
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bin_data = list(bin_string)
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bin_data = [int(x) for x in bin_data]
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# data size in bytes
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@ -78,17 +86,20 @@ class rom_base_bank(design):
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self.data = chunked_data
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self.cols = bits_per_row
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self.rows = int(num_words / (self.words_per_row))
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debug.info(1, "Read rom binary: length {0} bytes, {1} words, set number of cols to {2}, rows to {3}, with {4} words per row".format(data_size, num_words, self.cols, self.rows, self.words_per_row))
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# print("hex: {0}, binary: {1}, chunked: {2}".format(hex_data, bin_data, chunked_data))
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def create_netlist(self):
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self.add_modules()
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# self.add_pins()
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self.add_pins()
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print("Creating ROM bank instances")
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self.create_instances()
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def create_layout(self):
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print("Creating ROM bank instances")
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self.create_instances()
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print("Placing ROM bank instances")
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self.place_instances()
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@ -101,13 +112,12 @@ class rom_base_bank(design):
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print("Routing clock signal")
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self.route_clock()
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self.route_array_outputs()
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# self.route_supplies()
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self.place_top_level_pins()
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self.route_supplies()
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self.height = self.array_inst.height
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self.width = self.array_inst.width
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self.add_boundary()
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print("Rom bank placement complete")
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def setup_layout_constants(self):
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self.route_layer_width = drc["minwidth_{}".format(self.route_stack[0])]
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@ -121,11 +131,11 @@ class rom_base_bank(design):
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self.add_pin("clk", "INPUT")
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self.add_pin("CS", "INPUT")
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for i in range(self.num_inputs):
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for i in range(self.row_bits + self.col_bits):
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self.add_pin("addr_{}".format(i), "INPUT")
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out_pins = []
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for j in range(self.rows):
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for j in range(self.word_size):
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out_pins.append("rom_out_{}".format(j))
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self.add_pin_list(out_pins, "OUTPUT")
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@ -155,12 +165,12 @@ class rom_base_bank(design):
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cols=self.cols)
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self.column_mux = factory.create(module_type="rom_column_mux_array",
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columns=self.cols,
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word_size=self.word_size,
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bitline_layer=self.interconnect_layer)
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tap_spacing=self.strap_spacing,
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bitline_layer=self.interconnect_layer,
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input_layer=self.bitline_layer)
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self.column_decode = factory.create(module_name="rom_column_decode",
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module_type="rom_decoder",
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@ -175,53 +185,35 @@ class rom_base_bank(design):
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clk_fanout=(self.col_bits + self.row_bits) * 2,
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height=self.column_decode.height )
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print("Col decode height of {}".format(self.column_decode.height))
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def create_instances(self):
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gnd = ["gnd"]
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vdd = ["vdd"]
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prechrg = ["precharge"]
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clk = ["clk_int"]
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array_pins = []
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decode_pins = []
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for bl in range(self.cols):
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name = "bl_{}".format(bl)
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array_pins.append(name)
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for wl in range(self.rows):
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name = "wl_{}".format(wl)
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array_pins.append(wl)
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array_pins.append("precharge")
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array_pins.append("vdd")
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array_pins.append("gnd")
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for addr in range(self.row_bits):
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name = "row_addr_{}".format(addr)
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decode_pins.append(name)
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for wl in range(self.rows):
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name = "wl_{}".format(wl)
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decode_pins.append(name)
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decode_pins.append("precharge")
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decode_pins.append("clk_int")
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decode_pins.append("vdd")
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decode_pins.append("gnd")
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bitlines = ["bl_{}".format(bl) for bl in range(self.cols)]
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select_lines = ["word_sel_{}".format(word) for word in range(self.words_per_row)]
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bitline_out = ["rom_out_{}".format(bl) for bl in range(self.word_size)]
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addr_lsb = ["col_addr_{}".format(addr) for addr in range(self.col_bits)]
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col_mux_pins = bitlines + select_lines + bitline_out + gnd
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wordlines = ["wl_{}".format(wl) for wl in range(self.rows)]
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addr_msb = ["addr_{}".format(addr + self.col_bits) for addr in range(self.row_bits)]
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addr_lsb = ["addr_{}".format(addr) for addr in range(self.col_bits)]
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select_lines = ["word_sel_{}".format(word) for word in range(self.words_per_row)]
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outputs = ["rom_out_{}".format(bl) for bl in range(self.word_size)]
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array_pins = bitlines + wordlines + prechrg + vdd + gnd
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row_decode_pins = addr_msb + wordlines + prechrg + clk + vdd + gnd
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col_decode_pins = addr_lsb + select_lines + prechrg + clk + vdd + gnd
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col_mux_pins = bitlines + select_lines + outputs + gnd
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self.array_inst = self.add_inst(name="rom_bit_array", mod=self.array)
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self.connect_inst(array_pins)
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self.decode_inst = self.add_inst(name="rom_row_decoder", mod=self.decode_array)
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self.connect_inst(decode_pins)
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self.connect_inst(row_decode_pins)
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self.control_inst = self.add_inst(name="rom_control", mod=self.control_logic)
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self.connect_inst(["clk", "CS", "precharge", "clk_int", "vdd", "gnd"])
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@ -269,7 +261,7 @@ class rom_base_bank(design):
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self.col_decode_inst.place(offset=self.col_decode_offset)
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def place_col_mux(self):
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mux_y_offset = self.array_inst.by() - self.mux_inst.height - self.route_layer_pitch
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mux_y_offset = self.array_inst.by() - self.mux_inst.height - 5 * self.route_layer_pitch
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mux_x_offset = self.array_inst.get_pin("bl_0_0").cx() - self.mux_inst.get_pin("bl_0").cx()
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self.mux_offset = vector(mux_x_offset, mux_y_offset)
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@ -298,7 +290,7 @@ class rom_base_bank(design):
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col_decode_pins = [self.col_decode_inst.get_pin("wl_{}".format(wl)) for wl in range(self.words_per_row)]
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sel_pins = [self.mux_inst.get_pin("sel_{}".format(wl)) for wl in range(self.words_per_row)]
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sel_pins.extend(col_decode_pins)
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self.connect_row_pins(self.array.bitline_layer, sel_pins, round=True)
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self.connect_row_pins(self.wordline_layer, sel_pins, round=True)
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@ -391,34 +383,49 @@ class rom_base_bank(design):
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self.add_path(self.array.bitline_layer, [bl_out, bl_mux])
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def place_top_level_pins(self):
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self.copy_layout_pin(self.control_inst, "CS", "CS")
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for i in range(self.word_size):
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self.copy_layout_pin(self.mux_inst, "bl_out_{}".format(i), "rom_out_{}".format(i))
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for lsb in range(self.col_bits):
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name = "addr_{}".format(lsb)
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self.copy_layout_pin(self.col_decode_inst, "A{}".format(lsb), name)
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for msb in range(self.col_bits, self.row_bits + self.col_bits):
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name = "addr_{}".format(msb)
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pin_num = msb - self.col_bits
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self.copy_layout_pin(self.decode_inst, "A{}".format(pin_num), name)
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def route_supplies(self):
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for inst in self.insts:
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if not inst.mod.name.__contains__("contact"):
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self.copy_layout_pin(inst, "vdd")
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self.copy_layout_pin(inst, "gnd")
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gnd_start = vector(self.array_inst.get_pins("gnd")[0].cx(),0)
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# gnd_start = vector(self.array_inst.get_pins("gnd")[0].cx(),0)
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decode_gnd = self.decode_inst.get_pin("gnd")
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decode_vdd = self.decode_inst.get_pin("vdd")
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array_vdd = self.array_inst.get_pin("vdd")
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# decode_gnd = self.decode_inst.get_pin("gnd")
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# decode_vdd = self.decode_inst.get_pin("vdd")
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# array_vdd = self.array_inst.get_pin("vdd")
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# self.add_segment_center("m1", gnd_start, decode_gnd.center())
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# # self.add_segment_center("m1", gnd_start, decode_gnd.center())
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self.add_power_pin("gnd", decode_vdd.center())
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self.add_power_pin("vdd", decode_gnd.center())
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# self.add_power_pin("gnd", decode_vdd.center())
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# self.add_power_pin("vdd", decode_gnd.center())
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vdd_start = vector(array_vdd.lx() + 0.5 * self.via1_space, array_vdd.cy())
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end = vector(decode_vdd.lx(), vdd_start.y)
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# vdd_start = vector(array_vdd.lx() + 0.5 * self.via1_space, array_vdd.cy())
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# end = vector(decode_vdd.lx(), vdd_start.y)
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self.add_segment_center(self.interconnect_layer, vdd_start, end)
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self.add_via_stack_center(vdd_start, "m1", self.interconnect_layer)
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# self.add_segment_center(self.interconnect_layer, vdd_start, end)
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# self.add_via_stack_center(vdd_start, "m1", self.interconnect_layer)
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vdd_start = vector(decode_vdd.cx(), vdd_start.y)
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# vdd_start = vector(decode_vdd.cx(), vdd_start.y)
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self.add_segment_center(self.interconnect_layer, vdd_start, decode_vdd.center())
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# self.add_segment_center(self.interconnect_layer, vdd_start, decode_vdd.center())
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@ -80,7 +80,7 @@ class rom_base_cell(design):
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# height = self.base_width - min(self.cell_diffusion_offset, 0) - min(self.poly_active_offset, 0) - min(self.poly_tap_offset, 0)
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# make the cells square so the pitch of wordlines will match bitlines
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print("height: {0} width: {1}".format(height, width))
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# print("height: {0} width: {1}".format(height, width))
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if width > height:
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self.width = width
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self.height = width
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@ -57,19 +57,13 @@ class rom_column_mux(pgate):
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self.place_ptx()
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# cell = factory.create(module_type=OPTS.bitcell)
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# if(cell_props.use_strap == True and OPTS.num_ports == 1):
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# strap = factory.create(module_type=cell_props.strap_module, version=cell_props.strap_version)
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# precharge_width = cell.width + strap.width
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# else:
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# precharge_width = cell.width
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self.width = self.bitcell.width
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self.height = self.nmos_lower.uy() + self.pin_height
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self.connect_poly()
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self.add_bitline_pins()
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self.connect_bitlines()
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# self.add_pn_wells()
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self.add_pn_wells()
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def add_ptx(self):
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self.bitcell = factory.create(module_type="rom_base_cell")
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@ -107,7 +101,7 @@ class rom_column_mux(pgate):
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def place_ptx(self):
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""" Create the two pass gate NMOS transistors to switch the bitlines"""
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""" Create the pass gate NMOS transistor to switch the bitline """
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# Space it in the center
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nmos_lower_position = self.nmos.active_offset.scale(0, 1) \
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@ -148,7 +142,9 @@ class rom_column_mux(pgate):
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nmos_lower_s_pin = self.nmos_lower.get_pin("S")
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nmos_lower_d_pin = self.nmos_lower.get_pin("D")
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self.add_via_stack_center(from_layer=nmos_lower_s_pin.layer,
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to_layer=self.input_layer,
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offset=nmos_lower_s_pin.center())
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self.add_via_stack_center(from_layer=nmos_lower_d_pin.layer,
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to_layer=self.output_layer,
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@ -160,14 +156,14 @@ class rom_column_mux(pgate):
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+ nmos_lower_s_pin.uc().scale(0, 0.5)
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mid2 = bl_pin.bc().scale(0, 0.4) \
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+ nmos_lower_s_pin.uc().scale(1, 0.5)
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self.add_path(self.col_mux_stack[2],
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self.add_path(self.input_layer,
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[bl_pin.bc(), mid1, mid2, nmos_lower_s_pin.center()])
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# halfway up, move over
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mid1 = bl_out_pin.uc().scale(1, 0.4) \
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+ nmos_lower_d_pin.bc().scale(0, 0.4)
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mid2 = bl_out_pin.uc().scale(0, 0.4) \
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+ nmos_lower_d_pin.bc().scale(1, 0.4)
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self.add_path(self.col_mux_stack[0],
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self.add_path(self.output_layer,
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[bl_out_pin.uc(), mid1, mid2, nmos_lower_d_pin.center()])
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@ -197,7 +193,7 @@ class rom_column_mux(pgate):
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# rbc_width = self.bitcell.width
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# Add it to the right, aligned in between the two tx
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active_pos = vector(self.bitcell.width,
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self.nmos_upper.by() - 0.5 * self.poly_space)
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self.nmos_lower.uy() + self.active_contact.height + self.active_space)
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self.add_via_center(layers=self.active_stack,
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offset=active_pos,
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@ -205,16 +201,17 @@ class rom_column_mux(pgate):
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well_type="p")
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# If there is a li layer, include it in the power stack
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self.add_via_center(layers=self.col_mux_stack,
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self.add_via_stack_center(from_layer=self.active_stack[2],
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to_layer=self.supply_stack[0],
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offset=active_pos)
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self.add_layout_pin_rect_center(text="gnd",
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layer="m1",
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layer=self.supply_stack[0],
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offset=active_pos)
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# Add well enclosure over all the tx and contact
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if "pwell" in layer:
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self.add_rect(layer="pwell",
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offset=vector(0, 0),
|
||||
width=rbc_width,
|
||||
height=self.height)
|
||||
# if "pwell" in layer:
|
||||
# self.add_rect(layer="pwell",
|
||||
# offset=vector(0, 0),
|
||||
# width=rbc_width,
|
||||
# height=self.height)
|
||||
|
|
|
|||
|
|
@ -20,7 +20,7 @@ class rom_column_mux_array(design):
|
|||
Array of column mux to read the bitlines from ROM, based on the RAM column mux
|
||||
"""
|
||||
|
||||
def __init__(self, name, columns, word_size, input_layer="m2", bitline_layer="m1", sel_layer="m2"):
|
||||
def __init__(self, name, columns, word_size, tap_spacing=4, input_layer="m2", bitline_layer="m1", sel_layer="m2"):
|
||||
super().__init__(name)
|
||||
debug.info(1, "Creating {0}".format(self.name))
|
||||
self.add_comment("cols: {0} word_size: {1} ".format(columns, word_size))
|
||||
|
|
@ -29,6 +29,7 @@ class rom_column_mux_array(design):
|
|||
self.word_size = word_size
|
||||
self.words_per_row = int(self.columns / self.word_size)
|
||||
self.input_layer = input_layer
|
||||
self.tap_spacing = tap_spacing
|
||||
# self.sel_layer = layer_props.column_mux_array.select_layer
|
||||
self.sel_layer = sel_layer
|
||||
|
||||
|
|
@ -44,14 +45,6 @@ class rom_column_mux_array(design):
|
|||
if not OPTS.netlist_only:
|
||||
self.create_layout()
|
||||
|
||||
def get_bl_name(self):
|
||||
bl_name = self.mux.get_bl_names()
|
||||
return bl_name
|
||||
|
||||
def get_br_name(self, port=0):
|
||||
br_name = self.mux.get_br_names()
|
||||
return br_name
|
||||
|
||||
def create_netlist(self):
|
||||
self.add_modules()
|
||||
self.add_pins()
|
||||
|
|
@ -61,12 +54,14 @@ class rom_column_mux_array(design):
|
|||
self.setup_layout_constants()
|
||||
self.place_array()
|
||||
self.add_routing()
|
||||
|
||||
# Find the highest shapes to determine height before adding well
|
||||
highest = self.find_highest_coords()
|
||||
self.height = highest.y
|
||||
self.add_layout_pins()
|
||||
if "pwell" in layer:
|
||||
self.add_enclosure(self.mux_inst, "pwell")
|
||||
|
||||
self.add_boundary()
|
||||
self.DRC_LVS()
|
||||
|
||||
|
|
@ -80,8 +75,8 @@ class rom_column_mux_array(design):
|
|||
self.add_pin("gnd")
|
||||
|
||||
def add_modules(self):
|
||||
self.mux = factory.create(module_type="rom_column_mux")
|
||||
|
||||
self.mux = factory.create(module_type="rom_column_mux", input_layer=self.input_layer, output_layer=self.bitline_layer)
|
||||
self.tap = factory.create(module_type="rom_poly_tap", add_tap=True)
|
||||
self.cell = factory.create(module_type="rom_base_cell")
|
||||
|
||||
def setup_layout_constants(self):
|
||||
|
|
@ -145,8 +140,12 @@ class rom_column_mux_array(design):
|
|||
|
||||
def add_horizontal_input_rail(self):
|
||||
""" Create address input rails below the mux transistors """
|
||||
tap_offset = 0
|
||||
for j in range(self.words_per_row):
|
||||
offset = vector(0, self.route_height + (j - self.words_per_row) * self.cell.width)
|
||||
if j % self.tap_spacing == 0 and j != 0:
|
||||
tap_offset += self.tap.pitch_offset
|
||||
offset = vector(0, self.route_height + tap_offset + (j - self.words_per_row) * self.cell.width)
|
||||
|
||||
self.add_layout_pin(text="sel_{}".format(j),
|
||||
layer=self.sel_layer,
|
||||
offset=offset,
|
||||
|
|
@ -208,6 +207,9 @@ class rom_column_mux_array(design):
|
|||
directions=self.via_directions)
|
||||
|
||||
|
||||
def add_taps(self):
|
||||
pass
|
||||
|
||||
|
||||
def graph_exclude_columns(self, column_include_num):
|
||||
"""
|
||||
|
|
|
|||
|
|
@ -19,11 +19,9 @@ class rom_control_logic(design):
|
|||
self.height = height
|
||||
if self.height is not None:
|
||||
|
||||
print("got height of {}".format(self.height))
|
||||
self.driver_height = 0.6 * self.height
|
||||
self.gate_height = 0.2 * self.height
|
||||
self.driver_height = 0.5 * self.height
|
||||
self.gate_height = 0.25 * self.height
|
||||
else:
|
||||
print("got none height")
|
||||
self.gate_height = 20 * self.m1_pitch
|
||||
self.driver_height = self.gate_height
|
||||
|
||||
|
|
@ -98,12 +96,11 @@ class rom_control_logic(design):
|
|||
def route_insts(self):
|
||||
|
||||
route_width = drc["minwidth_{}".format(self.route_stack[2])]
|
||||
|
||||
self.copy_layout_pin(self.buf_inst, "A", "clk_in")
|
||||
self.copy_layout_pin(self.buf_inst, "Zb", "clkb_out")
|
||||
self.copy_layout_pin(self.buf_inst, "Z", "clk_out")
|
||||
self.copy_layout_pin(self.driver_inst, "Z", "prechrg")
|
||||
self.copy_layout_pin(self.nand_inst, "B", "CS")
|
||||
self.copy_layout_pin(self.nand_inst, "A", "CS")
|
||||
self.copy_layout_pin(self.buf_inst, "gnd")
|
||||
self.copy_layout_pin(self.driver_inst, "vdd")
|
||||
self.copy_layout_pin(self.buf_inst, "vdd")
|
||||
|
|
|
|||
|
|
@ -112,17 +112,17 @@ class rom_decoder(design):
|
|||
cols=self.num_inputs)
|
||||
|
||||
|
||||
self.wordline_buf = factory.create(module_type="rom_wordline_driver_array", module_name="{}_wordline_buffer".format(self.name), \
|
||||
rows=self.num_outputs, \
|
||||
cols=self.cols,
|
||||
self.wordline_buf = factory.create(module_type="rom_wordline_driver_array", module_name="{}_wordline_buffer".format(self.name),
|
||||
rows=self.num_outputs,
|
||||
cols=ceil(self.cols * 0.5),
|
||||
invert_outputs=self.invert_outputs,
|
||||
tap_spacing=self.strap_spacing)
|
||||
|
||||
|
||||
self.array_mod = factory.create(module_type="rom_base_array", \
|
||||
module_name="{}_array".format(self.name), \
|
||||
cols=self.num_outputs, \
|
||||
rows=2 * self.num_inputs, \
|
||||
self.array_mod = factory.create(module_type="rom_base_array",
|
||||
module_name="{}_array".format(self.name),
|
||||
cols=self.num_outputs,
|
||||
rows=2 * self.num_inputs,
|
||||
bitmap=self.decode_map,
|
||||
strap_spacing = self.strap_spacing,
|
||||
bitline_layer=self.output_layer,
|
||||
|
|
|
|||
|
|
@ -109,7 +109,7 @@ class rom_precharge_array(design):
|
|||
|
||||
|
||||
def create_precharge_tx(self, col):
|
||||
name = "Xpmos_c{0}".format(col)
|
||||
name = "pmos_c{0}".format(col)
|
||||
pmos = self.add_inst(name=name, mod=self.pmos)
|
||||
self.array_insts.append(pmos)
|
||||
self.pmos_insts.append(pmos)
|
||||
|
|
|
|||
|
|
@ -88,7 +88,6 @@ class rom_wordline_driver_array(design):
|
|||
"""
|
||||
|
||||
if layer_props.wordline_driver.vertical_supply:
|
||||
print("copied")
|
||||
# self.route_vertical_pins("vdd", self.wld_inst)
|
||||
# self.route_vertical_pins("gnd", self.wld_inst)
|
||||
self.route_vertical_pins("vdd", [self], layer=self.supply_layer)
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@ import sys, os
|
|||
import openram
|
||||
from openram import OPTS
|
||||
from openram.sram_factory import factory
|
||||
import debug
|
||||
from openram import debug
|
||||
|
||||
|
||||
class rom_bank_test(openram_test):
|
||||
|
|
@ -21,8 +21,7 @@ class rom_bank_test(openram_test):
|
|||
def runTest(self):
|
||||
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
|
||||
openram.init_openram(config_file, is_unit_test=True)
|
||||
|
||||
debug.info(2, "Testing 4x4 array for rom cell")
|
||||
debug.info(1, "Testing 1kB rom cell")
|
||||
|
||||
a = factory.create(module_type="rom_base_bank", strap_spacing = 8, data_file="/openram/technology/rom_data_1kB", word_size=1)
|
||||
|
||||
|
|
@ -0,0 +1,36 @@
|
|||
#!/usr/bin/env python3
|
||||
# See LICENSE for licensing information.
|
||||
#
|
||||
# Copyright (c) 2016-2021 Regents of the University of California and The Board
|
||||
# of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
# (acting for and on behalf of Oklahoma State University)
|
||||
# All rights reserved.
|
||||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys, os
|
||||
|
||||
import openram
|
||||
from openram import OPTS
|
||||
from openram.sram_factory import factory
|
||||
from openram import debug
|
||||
|
||||
|
||||
class rom_bank_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
|
||||
openram.init_openram(config_file, is_unit_test=True)
|
||||
debug.info(1, "Testing 32 byte rom cell")
|
||||
|
||||
a = factory.create(module_type="rom_base_bank", strap_spacing = 8, data_file="/openram/technology/rom_data_64B", word_size=1)
|
||||
|
||||
self.local_check(a)
|
||||
openram.end_openram()
|
||||
|
||||
# run the test from the command line
|
||||
if __name__ == "__main__":
|
||||
(OPTS, args) = openram.parse_args()
|
||||
del sys.argv[1:]
|
||||
header(__file__, OPTS.tech_name)
|
||||
unittest.main(testRunner=debugTestRunner())
|
||||
Loading…
Reference in New Issue