add top level pins for sim

compiler/tests/05_rom_base_bank_1kB_test.py

@@ -13,7 +13,7 @@ import sys, os
 import openram
 from openram import OPTS
 from openram.sram_factory import factory
-import debug
+from openram import debug
 
 
 class rom_bank_test(openram_test):
@@ -21,8 +21,7 @@ class rom_bank_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
-
-        debug.info(2, "Testing 4x4 array for rom cell")
+        debug.info(1, "Testing 1kB rom cell")
 
         a = factory.create(module_type="rom_base_bank", strap_spacing = 8, data_file="/openram/technology/rom_data_1kB", word_size=1)
 

compiler/tests/05_rom_base_bank_small_test.py

@@ -0,0 +1,36 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys, os
+
+import openram
+from openram import OPTS
+from openram.sram_factory import factory
+from openram import debug
+
+
+class rom_bank_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        openram.init_openram(config_file, is_unit_test=True)
+        debug.info(1, "Testing 32 byte rom cell")
+
+        a = factory.create(module_type="rom_base_bank", strap_spacing = 8, data_file="/openram/technology/rom_data_64B", word_size=1)
+
+        self.local_check(a)
+        openram.end_openram()
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = openram.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())