diff --git a/compiler/bitcells/bitcell_base.py b/compiler/bitcells/bitcell_base.py
index 56c36b66..f0f562c6 100644
--- a/compiler/bitcells/bitcell_base.py
+++ b/compiler/bitcells/bitcell_base.py
@@ -101,11 +101,15 @@ class bitcell_base(design.design):
 
     def get_bitline_offset(self):
         self.bitline_names = ["bl", "br"]
+        found_bitlines = []
         self.bitline_offsets = []
         for i in range(len(self.bitline_names)):
             for text in self.gds.getTexts(layer["metal2"]):
-                if self.bitline_names[i] == text.textString.rstrip('\x00'):
-                    self.bitline_offsets.append(text.coordinates[0])
+                if not self.bitline_names[i] in found_bitlines:
+                    if self.bitline_names[i] == text.textString.rstrip('\x00'):
+                        self.bitline_offsets.append(text.coordinates[0])
+                        found_bitlines.append(self.bitline_names[i])
+                        continue
                 
         for i in range(len(self.bitline_offsets)):
             self.bitline_offsets[i]  = tuple([self.gds.info["units"][0] * x for x in self.bitline_offsets[i]])
diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py
index f53e91a6..3aa2765a 100644
--- a/compiler/characterizer/delay.py
+++ b/compiler/characterizer/delay.py
@@ -302,7 +302,10 @@ class delay(simulation):
         exclude_set = self.get_bl_name_search_exclusions()
         for int_net in [cell_bl, cell_br]:
             bl_names.append(self.get_alias_in_path(paths, int_net, cell_mod, exclude_set))
-                
+        #if OPTS.use_pex:
+        #    bank_num = 0
+        #    bl_names[0] = "bl_b{0}_{1}".format(bank_num, )
+        #    bl_names[1] = "br_b{0}_{1}".format(bank_num, )
         return bl_names[0], bl_names[1]         
 
     
diff --git a/compiler/characterizer/stimuli.py b/compiler/characterizer/stimuli.py
index 5d08fbf9..28a02472 100644
--- a/compiler/characterizer/stimuli.py
+++ b/compiler/characterizer/stimuli.py
@@ -57,6 +57,9 @@ class stimuli():
                     for col in range(OPTS.word_size):
                         self.sf.write("bitcell_Q_b{0}_r{1}_c{2} ".format(bank,row,col))
                         self.sf.write("bitcell_Q_bar_b{0}_r{1}_c{2} ".format(bank,row,col))
+                for col in range(OPTS.word_size):
+                    self.sf.write("bl_b{0}_c{2} ".format(bank, row,col))
+                    self.sf.write("br_b{0}_c{2} ".format(bank, row,col))
                 self.sf.write("s_en{0} ".format(bank))
         self.sf.write("{0}\n".format(model_name))
 
diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py
index 1a8d220b..5fc510b7 100644
--- a/compiler/sram/sram_base.py
+++ b/compiler/sram/sram_base.py
@@ -115,8 +115,8 @@ class sram_base(design, verilog, lef):
                 self.add_layout_pin_rect_center("bitcell_Q_b{0}_r{1}_c{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , storage_layer_name, Q) 
                 self.add_layout_pin_rect_center("bitcell_Q_bar_b{0}_r{1}_c{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)), storage_layer_name, Q_bar)
 
-                self.add_layout_pin_rect_center("bitcell_bl_b{0}_c{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , bitline_layer_name, bl) 
-                self.add_layout_pin_rect_center("bitcell_br_b{0}_c{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)), bitline_layer_name, br)
+                self.add_layout_pin_rect_center("bl_b{0}_{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , bitline_layer_name, bl)
+                self.add_layout_pin_rect_center("br_b{0}_{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)), bitline_layer_name, br)
 
            
             
diff --git a/compiler/verify/magic.py b/compiler/verify/magic.py
index fa219e77..29014797 100644
--- a/compiler/verify/magic.py
+++ b/compiler/verify/magic.py
@@ -419,6 +419,9 @@ def correct_port(name, output_file_name, ref_file_name):
             for col in range(OPTS.word_size):
                 bitcell_list += "bitcell_Q_b{0}_r{1}_c{2} ".format(bank, row,col)
                 bitcell_list += "bitcell_Q_bar_b{0}_r{1}_c{2} ".format(bank, row,col)
+        for col in range(OPTS.word_size):
+                bitcell_list += "bl_b{0}_c{2} ".format(bank, row,col)
+                bitcell_list += "br_b{0}_c{2} ".format(bank, row,col)
     bitcell_list += "\n"
 
     control_list = "+ "