From 734be5403e4bab54e0f9c7f03fefe2a9f264bbf3 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Wed, 24 Jun 2026 11:27:28 -0700 Subject: [PATCH] fix naming for spare cols --- compiler/modules/sram_1bank.py | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/compiler/modules/sram_1bank.py b/compiler/modules/sram_1bank.py index 7d1aec3f..d0c6c638 100644 --- a/compiler/modules/sram_1bank.py +++ b/compiler/modules/sram_1bank.py @@ -662,7 +662,12 @@ class sram_1bank(design, verilog, lef): inputs = [] outputs = [] for bit in range(self.num_spare_cols): - inputs.append("spare_wen{}[{}]".format(port, bit)) + # The top-level pin is a scalar (spare_wen{port}) when there is + # a single spare column, so drop the 1-bit bus index to match it. + if self.num_spare_cols == 1: + inputs.append("spare_wen{}".format(port)) + else: + inputs.append("spare_wen{}[{}]".format(port, bit)) outputs.append("bank_spare_wen{}_{}".format(port, bit)) self.connect_inst(inputs + outputs + ["clk_buf{}".format(port)] + self.ext_supplies)