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Merge branch 'dev' of https://github.com/mguthaus/OpenRAM into dev

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This commit is contained in:
Matt Guthaus
2018-03-02 10:30:16 -08:00
parent ae2dbb4cd5 2f352c905f
commit 7293eb33bc
30 changed files with 227 additions and 18 deletions
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technology/freepdk45/tech/tech.py
+15
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@@ -283,6 +283,21 @@ spice["dff_delay"] = 20.5 # DFF Clk-to-q delay in ps
spice["dff_slew"] = 13.1 # DFF output slew in ps w/ no load
spice["dff_in_cap"] = 0.2091 # Input capacitance of ms_flop (Din) [Femto-farad]
# analytical power parameters, many values are temporary
spice["bitcell_leakage"] = 1 # Leakage power of a single bitcell in nW
spice["inv_leakage"] = 1 # Leakage power of inverter in nW
spice["nand2_leakage"] = 1 # Leakage power of 2-input nand in nW
spice["nand3_leakage"] = 1 # Leakage power of 3-input nand in nW
spice["nor2_leakage"] = 1 # Leakage power of 2-input nor in nW
spice["msflop_leakage"] = 1 # Leakage power of flop in nW
spice["flop_para_cap"] = 2 # Parasitic Output capacitance in fF
spice["default_event_rate"] = 100 # Default event activity of every gate. MHz
spice["flop_transisition_prob"] = .5 # Transition probability of inverter.
spice["inv_transisition_prob"] = .5 # Transition probability of inverter.
spice["nand2_transisition_prob"] = .1875 # Transition probability of 2-input nand.
spice["nand3_transisition_prob"] = .1094 # Transition probability of 3-input nand.
spice["nor2_transisition_prob"] = .1875 # Transition probability of 2-input nor.
###################################################
##END Spice Simulation Parameters
technology/scn3me_subm/models/ff/nmos.sp
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+1 -1
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@@ -5,6 +5,6 @@
* models from MOSIS or SCN3ME
*********************************************
.MODEL n NMOS (LEVEL=49 VTHO=0.669845 KP=113.7771E-6
.MODEL n NMOS (LEVEL=49 VTHO=0.669845
+ NSUB=6E16 U0=461 K1=0.5705 TOX=13.9n VERSION=3.3.0)
technology/scn3me_subm/models/ff/pmos.sp
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+1 -1
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@@ -5,5 +5,5 @@
* models from MOSIS or SCN3ME
*********************************************
.MODEL p PMOS (LEVEL=49 VTHO=-0.322431 KP=366.0244-6
.MODEL p PMOS (LEVEL=49 VTHO=-0.322431
+ NSUB=6E16 U0=212 K1=0.0821 TOX=13.9n VERSION=3.3.0)
technology/scn3me_subm/models/nom/nmos.sp
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+1 -1
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@@ -5,5 +5,5 @@
* models from MOSIS or SCN3ME
*********************************************
.MODEL n NMOS (LEVEL=49 VTHO=0.669845 KP=113.7771E-6
.MODEL n NMOS (LEVEL=49 VTHO=0.669845
+ NSUB=6E16 U0=458 K1=0.5705 TOX=13.9n VERSION=3.3.0)
technology/scn3me_subm/models/nom/pmos.sp
Vendored
+1 -1
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@@ -5,5 +5,5 @@
* models from MOSIS or SCN3ME
*********************************************
.MODEL p PMOS (LEVEL=49 VTHO=-0.322431 KP=366.0244-6
.MODEL p PMOS (LEVEL=49 VTHO=-0.322431
+ NSUB=6E16 U0=212 K1=0.0821 TOX=13.9n VERSION=3.3.0)
technology/scn3me_subm/models/ss/nmos.sp
Vendored
+1 -1
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@@ -5,6 +5,6 @@
* models from MOSIS or SCN3ME
*********************************************
.MODEL n NMOS (LEVEL=49 VTHO=0.669845 KP=113.7771E-6
.MODEL n NMOS (LEVEL=49 VTHO=0.669845
+ NSUB=6E16 U0=460 K1=0.5705 TOX=13.9n VERSION=3.3.0)
technology/scn3me_subm/models/ss/pmos.sp
Vendored
+1 -1
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@@ -5,5 +5,5 @@
* models from MOSIS or SCN3ME
*********************************************
.MODEL p PMOS (LEVEL=49 VTHO=-0.322431 KP=366.0244-6
.MODEL p PMOS (LEVEL=49 VTHO=-0.322431
+ NSUB=6E16 U0=212 K1=0.0821 TOX=13.9n VERSION=3.3.0)
technology/scn3me_subm/tech/tech.py
+14
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@@ -246,7 +246,21 @@ spice["dff_delay"] = 20.5 # DFF Clk-to-q delay in ps
spice["dff_slew"] = 13.1 # DFF output slew in ps w/ no load
spice["dff_in_cap"] = 9.8242 # Input capacitance of ms_flop (Din) [Femto-farad]
# analytical power parameters, many values are temporary
spice["bitcell_leakage"] = 1 # Leakage power of a single bitcell in nW
spice["inv_leakage"] = 1 # Leakage power of inverter in nW
spice["nand2_leakage"] = 1 # Leakage power of 2-input nand in nW
spice["nand3_leakage"] = 1 # Leakage power of 3-input nand in nW
spice["nor2_leakage"] = 1 # Leakage power of 2-input nor in nW
spice["msflop_leakage"] = 1 # Leakage power of flop in nW
spice["flop_para_cap"] = 2 # Parasitic Output capacitance in fF
spice["default_event_rate"] = 100 # Default event activity of every gate. MHz
spice["flop_transisition_prob"] = .5 # Transition probability of inverter.
spice["inv_transisition_prob"] = .5 # Transition probability of inverter.
spice["nand2_transisition_prob"] = .1875 # Transition probability of 2-input nand.
spice["nand3_transisition_prob"] = .1094 # Transition probability of 3-input nand.
spice["nor2_transisition_prob"] = .1875 # Transition probability of 2-input nor.
###################################################
##END Spice Simulation Parameters
###################################################