Merge branch 'dev' into wlbuffer

compiler/modules/dummy_array.py

@@ -101,16 +101,6 @@ class dummy_array(bitcell_base_array):
                     self.copy_layout_pin(inst, pin_name)
 
     def input_load(self):
+        # FIXME: This appears to be old code from previous characterization. Needs to be updated.
         wl_wire = self.gen_wl_wire()
         return wl_wire.return_input_cap()
-
-    def get_wordline_cin(self):
-        """ 
-        Get the relative input capacitance from the 
-        wordline connections in all the bitcell 
-        """
-        # A single wordline is connected to all the bitcells
-        # in a single row meaning the capacitance depends on the # of columns
-        bitcell_wl_cin = self.cell.get_wl_cin()
-        total_cin = bitcell_wl_cin * self.column_size
-        return total_cin