From f0958b0b118a6181705bd97dc18098f345e8719a Mon Sep 17 00:00:00 2001 From: jcirimel Date: Wed, 18 Dec 2019 03:03:13 -0800 Subject: [PATCH 01/31] squashed update of pex progress due to timezone error --- compiler/base/geometry.py | 102 +++++++++++- compiler/base/hierarchy_layout.py | 2 + compiler/bitcells/bitcell_base.py | 35 ++++- compiler/bitcells/pbitcell.py | 19 ++- compiler/characterizer/delay.py | 8 +- compiler/characterizer/stimuli.py | 5 + compiler/modules/bank.py | 5 +- compiler/modules/control_logic.py | 4 +- compiler/sram/sram_base.py | 38 +++++ compiler/verify/magic.py | 44 +++--- technology/scn4m_subm/mag_lib/cell_1rw_1r.mag | 137 ++++++++-------- technology/scn4m_subm/mag_lib/cell_1w_1r.mag | 137 ++++++++-------- technology/scn4m_subm/mag_lib/cell_6t.mag | 116 +++++++------- .../scn4m_subm/mag_lib/dummy_cell_1rw_1r.mag | 143 +++++++++-------- .../scn4m_subm/mag_lib/dummy_cell_1w_1r.mag | 143 +++++++++-------- .../scn4m_subm/mag_lib/dummy_cell_6t.mag | 112 ++++++------- .../mag_lib/replica_cell_1rw_1r.mag | 147 +++++++++--------- .../scn4m_subm/mag_lib/replica_cell_1w_1r.mag | 147 +++++++++--------- .../scn4m_subm/mag_lib/replica_cell_6t.mag | 116 +++++++------- 19 files changed, 813 insertions(+), 647 deletions(-) diff --git a/compiler/base/geometry.py b/compiler/base/geometry.py index 74b02f5f..1c037fdf 100644 --- a/compiler/base/geometry.py +++ b/compiler/base/geometry.py @@ -12,6 +12,8 @@ import debug from vector import vector import tech import math +import copy +import numpy as np from globals import OPTS from utils import round_to_grid @@ -221,9 +223,8 @@ class instance(geometry): self.mirror = mirror self.rotate = rotate self.update_boundary() - debug.info(3, "placing instance {}".format(self)) - - + debug.info(3, "placing instance {}".format(self)) + def get_pin(self,name,index=-1): """ Return an absolute pin that is offset and transformed based on this instance location. Index will return one of several pins.""" @@ -241,20 +242,109 @@ class instance(geometry): def get_num_pins(self, name): """ Return the number of pins of a given name """ return len(self.mod.get_pins(name)) - + def get_pins(self,name): """ Return an absolute pin that is offset and transformed based on this instance location. """ - + import copy pin = copy.deepcopy(self.mod.get_pins(name)) - + new_pins = [] for p in pin: p.transform(self.offset,self.mirror,self.rotate) new_pins.append(p) return new_pins + + def reverse_bitcell_transformation(self): + path = [] + bitcell_paths = [] + pex_offsets = [] + Q_offsets = [] + Q_bar_offsets = [] + + def walk_subtree(node): + path.append(node) + + if node.mod.name == 'pbitcell': + bitcell_paths.append(copy.copy(path)) + + Q_x = node.mod.get_normalized_storage_net_offset()[0][0] + Q_y = node.mod.get_normalized_storage_net_offset()[0][1] + + Q_bar_x = node.mod.get_normalized_storage_net_offset()[1][0] + Q_bar_y = node.mod.get_normalized_storage_net_offset()[1][1] + + if node.mirror == 'MX': + Q_y = -1 * Q_y + Q_bar_y = -1 * Q_bar_y + + Q_offsets.append([Q_x, Q_y]) + Q_bar_offsets.append([Q_bar_x, Q_bar_y]) + + + elif node.mod.insts is not []: + for instance in node.mod.insts: + walk_subtree(instance) + path.pop(-1) + + def calculate_transform(node): + #set up the rotation matrix + angle = math.radians(float(node.rotate)) + mRotate = np.array([[math.cos(angle),-math.sin(angle),0.0], + [math.sin(angle),math.cos(angle),0.0], + [0.0,0.0,1.0]]) + + #set up translation matrix + translateX = float(node.offset[0]) + translateY = float(node.offset[1]) + mTranslate = np.array([[1.0,0.0,translateX], + [0.0,1.0,translateY], + [0.0,0.0,1.0]]) + + #set up the scale matrix (handles mirror X) + scaleX = 1.0 + if(node.mirror == 'MX'): + scaleY = -1.0 + else: + scaleY = 1.0 + mScale = np.array([[scaleX,0.0,0.0], + [0.0,scaleY,0.0], + [0.0,0.0,1.0]]) + + return (mRotate, mScale, mTranslate) + + def apply_transform(mtransforms, uVector, vVector, origin): + origin = np.dot(mtransforms[0], origin) #rotate + uVector = np.dot(mtransforms[0], uVector) #rotate + vVector = np.dot(mtransforms[0], vVector) #rotate + origin = np.dot(mtransforms[1], origin) #scale + uVector = np.dot(mtransforms[1], uVector) #scale + vVector = np.dot(mtransforms[1], vVector) #scale + origin = np.dot(mtransforms[2], origin) + + return(uVector, vVector, origin) + + def apply_path_transform(path): + uVector = np.array([[1.0],[0.0],[0.0]]) + vVector = np.array([[0.0],[1.0],[0.0]]) + origin = np.array([[0.0],[0.0],[1.0]]) + + while(path): + instance = path.pop(-1) + mtransforms = calculate_transform(instance) + (uVector, vVector, origin) = apply_transform(mtransforms, uVector, vVector, origin) + + return (uVector, vVector, origin) + + walk_subtree(self) + for path in bitcell_paths: + vector_spaces = apply_path_transform(path) + origin = vector_spaces[2] + pex_offsets.append([origin[0], origin[1]]) + return(pex_offsets, Q_offsets, Q_bar_offsets) + def __str__(self): """ override print function output """ return "( inst: " + self.name + " @" + str(self.offset) + " mod=" + self.mod.name + " " + self.mirror + " R=" + str(self.rotate) + ")" diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index 2fea5c61..ae288d2e 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -1124,6 +1124,8 @@ class layout(): pdf.drawLayout() pdf.writeToFile(pdf_name) + + def print_attr(self): """Prints a list of attributes for the current layout object""" debug.info(0, diff --git a/compiler/bitcells/bitcell_base.py b/compiler/bitcells/bitcell_base.py index 5265904b..ea394548 100644 --- a/compiler/bitcells/bitcell_base.py +++ b/compiler/bitcells/bitcell_base.py @@ -8,6 +8,7 @@ import debug import design +from globals import OPTS import logical_effort from tech import parameter, drc @@ -78,7 +79,39 @@ class bitcell_base(design.design): fmt_str = "Storage nodes={} not found in spice file." debug.info(1, fmt_str.format(self.storage_nets)) return None - + + def get_storage_net_offset(self): + """ + Gets the location of the storage net labels to add top level + labels for pex simulation. + """ + #TODO: use getTexts to support custom bitcells + # If we generated the bitcell, we already know where Q and Q_bar are + #if OPTS.bitcell is not "pbitcell": + # self.storage_net_offsets = [] + # for net in get_storage_net_names: + # if net is "Q" or "Q_bar": + # for text in self.getTexts("metal1"): + # self.storage_net_offsets.append(text.offsetInMicrons) + return(self.storage_net_offsets) + + def get_normalized_storage_net_offset(self): + """ + Convert storage net offset to be relative to the bottom left corner + of the bitcell. This is useful for making sense of offsets outside + of the bitcell. + """ + + Q_x = self.storage_net_offsets[0][0] - self.leftmost_xpos + Q_y = self.storage_net_offsets[0][1] - self.botmost_ypos + Q_bar_x = self.storage_net_offsets[1][0] - self.leftmost_xpos + Q_bar_y = self.storage_net_offsets[1][1] - self.botmost_ypos + + normalized_storage_net_offset = [[Q_x,Q_y],[Q_bar_x,Q_bar_y]] + + return normalized_storage_net_offset + + def build_graph(self, graph, inst_name, port_nets): """ By default, bitcells won't be part of the graph. diff --git a/compiler/bitcells/pbitcell.py b/compiler/bitcells/pbitcell.py index bbfdf942..d14a36ed 100644 --- a/compiler/bitcells/pbitcell.py +++ b/compiler/bitcells/pbitcell.py @@ -26,7 +26,7 @@ class pbitcell(bitcell_base.bitcell_base): self.num_w_ports = OPTS.num_w_ports self.num_r_ports = OPTS.num_r_ports self.total_ports = self.num_rw_ports + self.num_w_ports + self.num_r_ports - + self.replica_bitcell = replica_bitcell self.dummy_bitcell = dummy_bitcell @@ -152,7 +152,7 @@ class pbitcell(bitcell_base.bitcell_base): self.Q_bar = "Q_bar" self.Q = "Q" self.storage_nets = [self.Q, self.Q_bar] - + def add_modules(self): """ Determine size of transistors and add ptx modules """ # if there are any read/write ports, @@ -353,6 +353,11 @@ class pbitcell(bitcell_base.bitcell_base): self.right_building_edge = right_inverter_xpos \ + self.inverter_nmos.active_width + def add_pex_labels(self, left_inverter_offset, right_inverter_offset): + self.add_label("Q", "metal1", left_inverter_offset) + self.add_label("Q_bar", "metal1", right_inverter_offset) + self.storage_net_offsets = [left_inverter_offset, right_inverter_offset] + def route_storage(self): """ Routes inputs and outputs of inverters to cross couple them """ # connect input (gate) of inverters @@ -399,6 +404,16 @@ class pbitcell(bitcell_base.bitcell_base): contact_offset_right.y) self.add_path("poly", [contact_offset_right, gate_offset_left]) + # add labels to cross couple inverter for extracted simulation + contact_offset_left_output = vector(self.inverter_nmos_left.get_pin("D").rc().x \ + + 0.5 * contact.poly.height, + self.cross_couple_upper_ypos) + + contact_offset_right_output = vector(self.inverter_nmos_right.get_pin("S").lc().x \ + - 0.5*contact.poly.height, + self.cross_couple_lower_ypos) + self.add_pex_labels(contact_offset_left_output, contact_offset_right_output) + def route_rails(self): """ Adds gnd and vdd rails and connects them to the inverters """ # Add rails for vdd and gnd diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index 2a8d5293..e64f9515 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -217,8 +217,12 @@ class delay(simulation): storage_names = cell_inst.mod.get_storage_net_names() debug.check(len(storage_names) == 2, ("Only inverting/non-inverting storage nodes" "supported for characterization. Storage nets={}").format(storage_names)) - q_name = cell_name+'.'+str(storage_names[0]) - qbar_name = cell_name+'.'+str(storage_names[1]) + if not OPTS.use_pex: + q_name = cell_name+'.'+str(storage_names[0]) + qbar_name = cell_name+'.'+str(storage_names[1]) + else: + q_name = "bitcell_Q_r{0}_c{1}".format(OPTS.num_words -1, OPTS.word_size-1) + qbar_name = "bitcell_Q_r{0}_c{1}".format(OPTS.num_words -1, OPTS.word_size-1) # Bit measures, measurements times to be defined later. The measurement names must be unique # but they is enforced externally diff --git a/compiler/characterizer/stimuli.py b/compiler/characterizer/stimuli.py index 58a9e3ed..e565fb5f 100644 --- a/compiler/characterizer/stimuli.py +++ b/compiler/characterizer/stimuli.py @@ -51,6 +51,11 @@ class stimuli(): self.sf.write("X{0} ".format(model_name)) for pin in pins: self.sf.write("{0} ".format(pin)) + if OPTS.use_pex: + for row in range(0,OPTS.num_words): + for col in range(0,OPTS.word_size): + self.sf.write("bitcell_Q_r{0}_c{1} ".format(row,col)) + self.sf.write("bitcell_Q_bar_r{0}_c{1} ".format(row,col)) self.sf.write("{0}\n".format(model_name)) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 3e105d09..0fe40ea8 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -75,8 +75,7 @@ class bank(design.design): self.bank_array_ll = self.offset_all_coordinates().scale(-1,-1) self.bank_array_ur = self.bitcell_array_inst.ur() self.bank_array_ul = self.bitcell_array_inst.ul() - - + self.DRC_LVS() def add_pins(self): @@ -968,7 +967,7 @@ class bank(design.design): stage_effort_list += self.port_address.wordline_driver.determine_wordline_stage_efforts(wordline_cout,inp_is_rise) return stage_effort_list - + def get_wl_en_cin(self): """Get the relative capacitance of all the clk connections in the bank""" #wl_en only used in the wordline driver. diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index 3256c9ac..354179ca 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -789,7 +789,7 @@ class control_logic(design.design): layer="metal1", start=out_pin.center(), end=right_pos) - + def route_supply(self): @@ -847,7 +847,7 @@ class control_logic(design.design): height=pin.height(), width=pin.width()) - + def get_delays_to_wl(self): """Get the delay (in delay units) of the clk to a wordline in the bitcell array""" debug.check(self.sram.all_mods_except_control_done, "Cannot calculate sense amp enable delay unless all module have been added.") diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index 2a4983b6..547ba517 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -18,6 +18,7 @@ from design import design from verilog import verilog from lef import lef from sram_factory import factory +from tech import drc import logical_effort class sram_base(design, verilog, lef): @@ -85,6 +86,41 @@ class sram_base(design, verilog, lef): self.add_pin("vdd","POWER") self.add_pin("gnd","GROUND") + def add_global_pex_labels(self): + """ + Add pex labels at the sram level for spice analysis + """ + + # add pex labels for bitcell + for bank_num in range(0,len(self.bank_insts)): + bank = self.bank_insts[bank_num] + pex_offsets = bank.reverse_bitcell_transformation() + + bank_offset = pex_offsets[0] # offset bank relative to sram + Q_offset = pex_offsets[1] # offset of storage relative to bank + Q_bar_offset = pex_offsets[2] # offset of storage relative to bank + + layer = "metal1" + + for i in range(0,len(bank_offset)): + + Q = [bank_offset[i][0] + Q_offset[i][0], bank_offset[i][1] + Q_offset[i][1]] + Q_bar = [bank_offset[i][0] + Q_bar_offset[i][0], bank_offset[i][1] + Q_bar_offset[i][1]] + + self.add_layout_pin_rect_center("bitcell_Q_b{0}_r{1}_c{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , layer, Q) + self.add_layout_pin_rect_center("bitcell_Q_bar_b{0}_r{1}_c{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)), layer, Q_bar) + + # add pex labels for control logic + for i in range (0,len(self.control_logic_insts)): + control_logic_offset = self.control_logic_insts[i].offset + for output in self.control_logic_insts[i].mod.output_list: + pin = self.control_logic_insts[i].mod.get_pin(output) + offset = [control_logic_offset[0] + pin.center()[0], control_logic_offset[1] + pin.center()[1]] + self.add_layout_pin_rect_center("{0}{1}".format(pin.name,i), "metal1", offset) + + + + def create_netlist(self): """ Netlist creation """ @@ -126,6 +162,8 @@ class sram_base(design, verilog, lef): self.width = highest_coord[0] self.height = highest_coord[1] + self.add_global_pex_labels() + start_time = datetime.now() # We only enable final verification if we have routed the design self.DRC_LVS(final_verification=OPTS.route_supplies, top_level=True) diff --git a/compiler/verify/magic.py b/compiler/verify/magic.py index 63aeaabe..fb0bc452 100644 --- a/compiler/verify/magic.py +++ b/compiler/verify/magic.py @@ -80,12 +80,12 @@ def write_magic_script(cell_name, extract=False, final_verification=False): f.write(pre+"ext2spice renumber off\n") f.write(pre+"ext2spice scale off\n") f.write(pre+"ext2spice blackbox on\n") - f.write(pre+"ext2spice subcircuit top auto\n") + f.write(pre+"ext2spice subcircuit top on\n") f.write(pre+"ext2spice global off\n") # Can choose hspice, ngspice, or spice3, # but they all seem compatible enough. - #f.write(pre+"ext2spice format ngspice\n") + f.write(pre+"ext2spice format ngspice\n") f.write(pre+"ext2spice {}\n".format(cell_name)) f.write("quit -noprompt\n") f.write("EOF\n") @@ -309,7 +309,7 @@ def run_pex(name, gds_name, sp_name, output=None, final_verification=False): out_errors = find_error(results) debug.check(os.path.isfile(output),"Couldn't find PEX extracted output.") - correct_port(name,output,sp_name) + #correct_port(name,output,sp_name) return out_errors def write_batch_pex_rule(gds_name,name,sp_name,output): @@ -375,13 +375,13 @@ def write_script_pex_rule(gds_name,cell_name,output): else: pre = "" f.write(pre+"extract\n".format(cell_name)) - #f.write(pre+"ext2spice hierarchy on\n") - #f.write(pre+"ext2spice format ngspice\n") - #f.write(pre+"ext2spice renumber off\n") - #f.write(pre+"ext2spice scale off\n") - #f.write(pre+"ext2spice blackbox on\n") + f.write(pre+"ext2spice hierarchy on\n") + f.write(pre+"ext2spice format ngspice\n") + f.write(pre+"ext2spice renumber off\n") + f.write(pre+"ext2spice scale off\n") + f.write(pre+"ext2spice blackbox on\n") f.write(pre+"ext2spice subcircuit top on\n") - #f.write(pre+"ext2spice global off\n") + f.write(pre+"ext2spice global off\n") f.write(pre+"ext2spice {}\n".format(cell_name)) f.write("quit -noprompt\n") f.write("eof\n") @@ -404,31 +404,37 @@ def correct_port(name, output_file_name, ref_file_name): pex_file = open(output_file_name, "r") contents = pex_file.read() # locate the start of circuit definition line - match = re.search(".subckt " + str(name) + ".*", contents) + match = re.search(r'^\.subckt+[^M]*', contents, re.MULTILINE) match_index_start = match.start() - pex_file.seek(match_index_start) - rest_text = pex_file.read() - # locate the end of circuit definition line - match = re.search(r'\n', rest_text) - match_index_end = match.start() + match_index_end = match.end() # store the unchanged part of pex file in memory pex_file.seek(0) part1 = pex_file.read(match_index_start) - pex_file.seek(match_index_start + match_index_end) + pex_file.seek(match_index_end) part2 = pex_file.read() + + bitcell_list = "+ " + for row in range(0,OPTS.num_words): + for col in range(0,OPTS.word_size): + bitcell_list += "bitcell_Q_r{0}_c{1} ".format(row,col) + bitcell_list += "bitcell_Q_bar_r{0}_c{1} ".format(row,col) + bitcell_list += "\n" + + + part2 = bitcell_list + part2 pex_file.close() # obtain the correct definition line from the original spice file sp_file = open(ref_file_name, "r") contents = sp_file.read() - circuit_title = re.search(".SUBCKT " + str(name) + ".*\n", contents) + circuit_title = re.search(".SUBCKT " + str(name) + ".*", contents) circuit_title = circuit_title.group() sp_file.close() # write the new pex file with info in the memory output_file = open(output_file_name, "w") output_file.write(part1) - output_file.write(circuit_title) + output_file.write(circuit_title+'\n') output_file.write(part2) output_file.close() @@ -437,4 +443,4 @@ def print_drc_stats(): def print_lvs_stats(): debug.info(1,"LVS runs: {0}".format(num_lvs_runs)) def print_pex_stats(): - debug.info(1,"PEX runs: {0}".format(num_pex_runs)) + debug.info(1,"PEX runs: {0}".format(num_pex_runs)) \ No newline at end of file diff --git a/technology/scn4m_subm/mag_lib/cell_1rw_1r.mag b/technology/scn4m_subm/mag_lib/cell_1rw_1r.mag index 9aec1c5d..0f2cdadb 100644 --- a/technology/scn4m_subm/mag_lib/cell_1rw_1r.mag +++ b/technology/scn4m_subm/mag_lib/cell_1rw_1r.mag @@ -1,22 +1,31 @@ magic tech scmos -timestamp 1542220294 -<< nwell >> -rect 0 46 54 75 +timestamp 1572948731 << pwell >> rect 0 0 54 46 -<< ntransistor >> -rect 14 33 16 37 -rect 22 29 24 37 -rect 30 29 32 37 -rect 38 33 40 37 -rect 14 17 16 23 -rect 22 17 24 23 -rect 30 17 32 23 -rect 38 17 40 23 -<< ptransistor >> -rect 22 54 24 57 -rect 30 54 32 57 +<< nwell >> +rect 0 46 54 75 +<< polysilicon >> +rect 22 57 24 60 +rect 30 57 32 60 +rect 22 44 24 54 +rect 30 51 32 54 +rect 31 47 32 51 +rect 14 37 16 44 +rect 22 40 23 44 +rect 22 37 24 40 +rect 30 37 32 47 +rect 38 37 40 44 +rect 14 31 16 33 +rect 38 31 40 33 +rect 14 23 16 24 +rect 22 23 24 29 +rect 30 23 32 29 +rect 38 23 40 24 +rect 14 15 16 17 +rect 22 15 24 17 +rect 30 15 32 17 +rect 38 15 40 17 << ndiffusion >> rect 13 33 14 37 rect 16 33 17 37 @@ -41,46 +50,6 @@ rect 21 54 22 57 rect 24 54 25 57 rect 29 54 30 57 rect 32 54 33 57 -<< ndcontact >> -rect 9 33 13 37 -rect 17 33 21 37 -rect 25 29 29 37 -rect 33 33 37 37 -rect 41 33 45 37 -rect 25 17 29 23 -<< pdcontact >> -rect 17 54 21 58 -rect 33 54 37 58 -<< psubstratepcontact >> -rect 25 9 29 13 -<< polysilicon >> -rect 22 57 24 60 -rect 30 57 32 60 -rect 22 44 24 54 -rect 30 51 32 54 -rect 31 47 32 51 -rect 14 37 16 44 -rect 22 40 23 44 -rect 22 37 24 40 -rect 30 37 32 47 -rect 38 37 40 44 -rect 14 31 16 33 -rect 38 31 40 33 -rect 14 23 16 24 -rect 22 23 24 29 -rect 30 23 32 29 -rect 38 23 40 24 -rect 14 15 16 17 -rect 22 15 24 17 -rect 30 15 32 17 -rect 38 15 40 17 -<< polycontact >> -rect 27 47 31 51 -rect 10 40 14 44 -rect 23 40 27 44 -rect 40 40 44 44 -rect 12 24 16 28 -rect 38 24 42 28 << metal1 >> rect 0 68 25 72 rect 29 68 54 72 @@ -102,20 +71,6 @@ rect 29 9 54 13 rect 0 2 16 6 rect 20 2 34 6 rect 38 2 54 6 -<< m2contact >> -rect 2 33 6 37 -rect 48 33 52 37 -rect 16 24 20 28 -rect 34 24 38 28 -rect 16 2 20 6 -rect 34 2 38 6 -<< pdm12contact >> -rect 25 54 29 58 -<< ndm12contact >> -rect 9 17 13 21 -rect 41 17 45 21 -<< nsm12contact >> -rect 25 68 29 72 << metal2 >> rect 2 37 6 72 rect 2 0 6 33 @@ -125,11 +80,47 @@ rect 9 0 13 17 rect 16 6 20 24 rect 34 6 38 24 rect 41 21 45 72 -rect 41 0 45 17 rect 48 37 52 72 +rect 41 0 45 17 rect 48 0 52 33 -<< comment >> -rect 0 0 54 70 +<< ntransistor >> +rect 14 33 16 37 +rect 22 29 24 37 +rect 30 29 32 37 +rect 38 33 40 37 +rect 14 17 16 23 +rect 22 17 24 23 +rect 30 17 32 23 +rect 38 17 40 23 +<< ptransistor >> +rect 22 54 24 57 +rect 30 54 32 57 +<< polycontact >> +rect 27 47 31 51 +rect 10 40 14 44 +rect 23 40 27 44 +rect 40 40 44 44 +rect 12 24 16 28 +rect 38 24 42 28 +<< ndcontact >> +rect 9 33 13 37 +rect 17 33 21 37 +rect 25 29 29 37 +rect 33 33 37 37 +rect 41 33 45 37 +rect 25 17 29 23 +<< pdcontact >> +rect 17 54 21 58 +rect 33 54 37 58 +<< m2contact >> +rect 2 33 6 37 +rect 48 33 52 37 +rect 16 24 20 28 +rect 34 24 38 28 +rect 16 2 20 6 +rect 34 2 38 6 +<< psubstratepcontact >> +rect 25 9 29 13 << labels >> rlabel metal1 19 63 19 63 1 wl0 rlabel metal1 19 70 19 70 5 vdd @@ -139,4 +130,6 @@ rlabel metal2 4 7 4 7 2 bl0 rlabel metal2 11 7 11 7 1 bl1 rlabel metal2 43 7 43 7 1 br1 rlabel metal2 50 7 50 7 8 br0 +rlabel metal1 19 49 19 49 1 Q +rlabel metal1 35 42 35 42 1 Q_bar << end >> diff --git a/technology/scn4m_subm/mag_lib/cell_1w_1r.mag b/technology/scn4m_subm/mag_lib/cell_1w_1r.mag index 9aec1c5d..91d06069 100644 --- a/technology/scn4m_subm/mag_lib/cell_1w_1r.mag +++ b/technology/scn4m_subm/mag_lib/cell_1w_1r.mag @@ -1,22 +1,31 @@ magic tech scmos -timestamp 1542220294 -<< nwell >> -rect 0 46 54 75 +timestamp 1572948787 << pwell >> rect 0 0 54 46 -<< ntransistor >> -rect 14 33 16 37 -rect 22 29 24 37 -rect 30 29 32 37 -rect 38 33 40 37 -rect 14 17 16 23 -rect 22 17 24 23 -rect 30 17 32 23 -rect 38 17 40 23 -<< ptransistor >> -rect 22 54 24 57 -rect 30 54 32 57 +<< nwell >> +rect 0 46 54 75 +<< polysilicon >> +rect 22 57 24 60 +rect 30 57 32 60 +rect 22 44 24 54 +rect 30 51 32 54 +rect 31 47 32 51 +rect 14 37 16 44 +rect 22 40 23 44 +rect 22 37 24 40 +rect 30 37 32 47 +rect 38 37 40 44 +rect 14 31 16 33 +rect 38 31 40 33 +rect 14 23 16 24 +rect 22 23 24 29 +rect 30 23 32 29 +rect 38 23 40 24 +rect 14 15 16 17 +rect 22 15 24 17 +rect 30 15 32 17 +rect 38 15 40 17 << ndiffusion >> rect 13 33 14 37 rect 16 33 17 37 @@ -41,46 +50,6 @@ rect 21 54 22 57 rect 24 54 25 57 rect 29 54 30 57 rect 32 54 33 57 -<< ndcontact >> -rect 9 33 13 37 -rect 17 33 21 37 -rect 25 29 29 37 -rect 33 33 37 37 -rect 41 33 45 37 -rect 25 17 29 23 -<< pdcontact >> -rect 17 54 21 58 -rect 33 54 37 58 -<< psubstratepcontact >> -rect 25 9 29 13 -<< polysilicon >> -rect 22 57 24 60 -rect 30 57 32 60 -rect 22 44 24 54 -rect 30 51 32 54 -rect 31 47 32 51 -rect 14 37 16 44 -rect 22 40 23 44 -rect 22 37 24 40 -rect 30 37 32 47 -rect 38 37 40 44 -rect 14 31 16 33 -rect 38 31 40 33 -rect 14 23 16 24 -rect 22 23 24 29 -rect 30 23 32 29 -rect 38 23 40 24 -rect 14 15 16 17 -rect 22 15 24 17 -rect 30 15 32 17 -rect 38 15 40 17 -<< polycontact >> -rect 27 47 31 51 -rect 10 40 14 44 -rect 23 40 27 44 -rect 40 40 44 44 -rect 12 24 16 28 -rect 38 24 42 28 << metal1 >> rect 0 68 25 72 rect 29 68 54 72 @@ -102,20 +71,6 @@ rect 29 9 54 13 rect 0 2 16 6 rect 20 2 34 6 rect 38 2 54 6 -<< m2contact >> -rect 2 33 6 37 -rect 48 33 52 37 -rect 16 24 20 28 -rect 34 24 38 28 -rect 16 2 20 6 -rect 34 2 38 6 -<< pdm12contact >> -rect 25 54 29 58 -<< ndm12contact >> -rect 9 17 13 21 -rect 41 17 45 21 -<< nsm12contact >> -rect 25 68 29 72 << metal2 >> rect 2 37 6 72 rect 2 0 6 33 @@ -125,11 +80,47 @@ rect 9 0 13 17 rect 16 6 20 24 rect 34 6 38 24 rect 41 21 45 72 -rect 41 0 45 17 rect 48 37 52 72 +rect 41 0 45 17 rect 48 0 52 33 -<< comment >> -rect 0 0 54 70 +<< ntransistor >> +rect 14 33 16 37 +rect 22 29 24 37 +rect 30 29 32 37 +rect 38 33 40 37 +rect 14 17 16 23 +rect 22 17 24 23 +rect 30 17 32 23 +rect 38 17 40 23 +<< ptransistor >> +rect 22 54 24 57 +rect 30 54 32 57 +<< polycontact >> +rect 27 47 31 51 +rect 10 40 14 44 +rect 23 40 27 44 +rect 40 40 44 44 +rect 12 24 16 28 +rect 38 24 42 28 +<< ndcontact >> +rect 9 33 13 37 +rect 17 33 21 37 +rect 25 29 29 37 +rect 33 33 37 37 +rect 41 33 45 37 +rect 25 17 29 23 +<< pdcontact >> +rect 17 54 21 58 +rect 33 54 37 58 +<< m2contact >> +rect 2 33 6 37 +rect 48 33 52 37 +rect 16 24 20 28 +rect 34 24 38 28 +rect 16 2 20 6 +rect 34 2 38 6 +<< psubstratepcontact >> +rect 25 9 29 13 << labels >> rlabel metal1 19 63 19 63 1 wl0 rlabel metal1 19 70 19 70 5 vdd @@ -139,4 +130,6 @@ rlabel metal2 4 7 4 7 2 bl0 rlabel metal2 11 7 11 7 1 bl1 rlabel metal2 43 7 43 7 1 br1 rlabel metal2 50 7 50 7 8 br0 +rlabel metal1 19 49 19 49 1 Q +rlabel metal1 35 42 35 42 1 Q_bar << end >> diff --git a/technology/scn4m_subm/mag_lib/cell_6t.mag b/technology/scn4m_subm/mag_lib/cell_6t.mag index bb9d943d..6b277af2 100644 --- a/technology/scn4m_subm/mag_lib/cell_6t.mag +++ b/technology/scn4m_subm/mag_lib/cell_6t.mag @@ -1,18 +1,28 @@ magic tech scmos -timestamp 1560809302 -<< nwell >> -rect -8 35 42 57 +timestamp 1572949512 << pwell >> rect -8 -2 42 35 -<< ntransistor >> -rect 7 16 9 24 -rect 29 16 31 24 -rect 10 9 14 11 -rect 24 9 28 11 -<< ptransistor >> -rect 7 43 11 46 -rect 27 43 31 46 +<< nwell >> +rect -8 35 42 57 +<< polysilicon >> +rect 7 46 11 48 +rect 27 46 31 48 +rect 7 41 11 43 +rect 7 27 9 41 +rect 27 40 31 43 +rect 15 39 31 40 +rect 19 38 31 39 +rect 7 26 21 27 +rect 7 25 24 26 +rect 7 24 9 25 +rect 29 24 31 38 +rect 7 14 9 16 +rect 17 11 21 12 +rect 29 14 31 16 +rect -2 9 10 11 +rect 14 9 24 11 +rect 28 9 36 11 << ndiffusion >> rect -2 22 7 24 rect 2 18 7 22 @@ -33,45 +43,6 @@ rect 2 43 7 46 rect 11 43 12 46 rect 26 43 27 46 rect 31 43 32 46 -<< ndcontact >> -rect -2 18 2 22 -rect 10 20 14 24 -rect 24 20 28 24 -rect 32 18 36 22 -rect 10 4 14 8 -rect 24 4 28 8 -<< pdcontact >> -rect -2 42 2 46 -rect 12 42 16 46 -rect 22 42 26 46 -rect 32 42 36 46 -<< psubstratepcontact >> -rect -2 28 2 32 -rect 32 28 36 32 -<< nsubstratencontact >> -rect 32 50 36 54 -<< polysilicon >> -rect 7 46 11 48 -rect 27 46 31 48 -rect 7 41 11 43 -rect 7 27 9 41 -rect 27 40 31 43 -rect 15 39 31 40 -rect 19 38 31 39 -rect 7 26 21 27 -rect 7 25 24 26 -rect 7 24 9 25 -rect 29 24 31 38 -rect 7 14 9 16 -rect 17 11 21 12 -rect 29 14 31 16 -rect -2 9 10 11 -rect 14 9 24 11 -rect 28 9 36 11 -<< polycontact >> -rect 15 35 19 39 -rect 21 26 25 30 -rect 17 12 21 16 << metal1 >> rect -2 50 15 54 rect 19 50 32 54 @@ -92,12 +63,6 @@ rect 32 22 36 28 rect -2 12 17 15 rect 21 12 36 15 rect -2 11 36 12 -<< m2contact >> -rect 15 50 19 54 -rect -2 35 2 39 -rect 32 35 36 39 -rect 6 4 10 8 -rect 20 4 24 8 << metal2 >> rect -2 39 2 54 rect -2 0 2 35 @@ -106,8 +71,41 @@ rect 6 0 10 4 rect 24 0 28 54 rect 32 39 36 54 rect 32 0 36 35 -<< bb >> -rect 0 0 34 52 +<< ntransistor >> +rect 7 16 9 24 +rect 29 16 31 24 +rect 10 9 14 11 +rect 24 9 28 11 +<< ptransistor >> +rect 7 43 11 46 +rect 27 43 31 46 +<< polycontact >> +rect 15 35 19 39 +rect 21 26 25 30 +rect 17 12 21 16 +<< ndcontact >> +rect -2 18 2 22 +rect 10 20 14 24 +rect 24 20 28 24 +rect 32 18 36 22 +rect 10 4 14 8 +rect 24 4 28 8 +<< pdcontact >> +rect -2 42 2 46 +rect 12 42 16 46 +rect 22 42 26 46 +rect 32 42 36 46 +<< m2contact >> +rect 15 50 19 54 +rect -2 35 2 39 +rect 32 35 36 39 +rect 6 4 10 8 +rect 20 4 24 8 +<< psubstratepcontact >> +rect -2 28 2 32 +rect 32 28 36 32 +<< nsubstratencontact >> +rect 32 50 36 54 << labels >> rlabel metal2 0 6 0 6 1 gnd rlabel metal2 34 6 34 6 1 gnd @@ -115,4 +113,6 @@ rlabel m2contact 17 52 17 52 5 vdd rlabel metal2 8 49 8 49 1 bl rlabel metal2 26 49 26 49 1 br rlabel metal1 4 13 4 13 1 wl +rlabel polycontact 23 28 23 28 1 Q_bar +rlabel polycontact 17 37 17 37 1 Q << end >> diff --git a/technology/scn4m_subm/mag_lib/dummy_cell_1rw_1r.mag b/technology/scn4m_subm/mag_lib/dummy_cell_1rw_1r.mag index 60e24aca..79b5daf0 100644 --- a/technology/scn4m_subm/mag_lib/dummy_cell_1rw_1r.mag +++ b/technology/scn4m_subm/mag_lib/dummy_cell_1rw_1r.mag @@ -1,63 +1,10 @@ magic tech scmos -timestamp 1562188987 -<< nwell >> -rect 0 46 54 75 +timestamp 1572949567 << pwell >> rect 0 0 54 46 -<< ntransistor >> -rect 14 33 16 37 -rect 22 29 24 37 -rect 30 29 32 37 -rect 38 33 40 37 -rect 14 17 16 23 -rect 22 17 24 23 -rect 30 17 32 23 -rect 38 17 40 23 -<< ptransistor >> -rect 22 54 24 57 -rect 30 54 32 57 -<< ndiffusion >> -rect 13 33 14 37 -rect 16 33 17 37 -rect 21 33 22 37 -rect 17 29 22 33 -rect 24 29 25 37 -rect 29 29 30 37 -rect 32 33 33 37 -rect 37 33 38 37 -rect 40 33 41 37 -rect 32 29 37 33 -rect 9 21 14 23 -rect 13 17 14 21 -rect 16 17 22 23 -rect 24 17 25 23 -rect 29 17 30 23 -rect 32 17 38 23 -rect 40 21 45 23 -rect 40 17 41 21 -<< pdiffusion >> -rect 21 54 22 57 -rect 24 54 25 57 -rect 29 54 30 57 -rect 32 54 33 57 -<< ndcontact >> -rect 9 33 13 37 -rect 17 33 21 37 -rect 25 29 29 37 -rect 33 33 37 37 -rect 41 33 45 37 -rect 9 17 13 21 -rect 25 17 29 23 -rect 41 17 45 21 -<< pdcontact >> -rect 17 54 21 58 -rect 25 54 29 58 -rect 33 54 37 58 -<< psubstratepcontact >> -rect 25 9 29 13 -<< nsubstratencontact >> -rect 25 68 29 72 +<< nwell >> +rect 0 46 54 75 << polysilicon >> rect 22 57 24 60 rect 30 57 32 60 @@ -79,13 +26,30 @@ rect 14 15 16 17 rect 22 15 24 17 rect 30 15 32 17 rect 38 15 40 17 -<< polycontact >> -rect 27 47 31 51 -rect 10 40 14 44 -rect 23 40 27 44 -rect 40 40 44 44 -rect 12 24 16 28 -rect 38 24 42 28 +<< ndiffusion >> +rect 13 33 14 37 +rect 16 33 17 37 +rect 21 33 22 37 +rect 17 29 22 33 +rect 24 29 25 37 +rect 29 29 30 37 +rect 32 33 33 37 +rect 37 33 38 37 +rect 40 33 41 37 +rect 32 29 37 33 +rect 9 21 14 23 +rect 13 17 14 21 +rect 16 17 22 23 +rect 24 17 25 23 +rect 29 17 30 23 +rect 32 17 38 23 +rect 40 21 45 23 +rect 40 17 41 21 +<< pdiffusion >> +rect 25 57 29 58 +rect 21 54 22 57 +rect 24 54 30 57 +rect 32 54 33 57 << metal1 >> rect 0 68 25 72 rect 29 68 54 72 @@ -107,13 +71,6 @@ rect 29 9 54 13 rect 0 2 16 6 rect 20 2 34 6 rect 38 2 54 6 -<< m2contact >> -rect 25 68 29 72 -rect 25 54 29 58 -rect 16 24 20 28 -rect 34 24 38 28 -rect 16 2 20 6 -rect 34 2 38 6 << metal2 >> rect 2 0 6 72 rect 9 0 13 72 @@ -122,8 +79,48 @@ rect 16 6 20 24 rect 34 6 38 24 rect 41 0 45 72 rect 48 0 52 72 -<< comment >> -rect 0 0 54 70 +<< ntransistor >> +rect 14 33 16 37 +rect 22 29 24 37 +rect 30 29 32 37 +rect 38 33 40 37 +rect 14 17 16 23 +rect 22 17 24 23 +rect 30 17 32 23 +rect 38 17 40 23 +<< ptransistor >> +rect 22 54 24 57 +rect 30 54 32 57 +<< polycontact >> +rect 27 47 31 51 +rect 10 40 14 44 +rect 23 40 27 44 +rect 40 40 44 44 +rect 12 24 16 28 +rect 38 24 42 28 +<< ndcontact >> +rect 9 33 13 37 +rect 17 33 21 37 +rect 25 29 29 37 +rect 33 33 37 37 +rect 41 33 45 37 +rect 9 17 13 21 +rect 25 17 29 23 +rect 41 17 45 21 +<< pdcontact >> +rect 17 54 21 58 +rect 33 54 37 58 +<< m2contact >> +rect 25 68 29 72 +rect 25 54 29 58 +rect 16 24 20 28 +rect 34 24 38 28 +rect 16 2 20 6 +rect 34 2 38 6 +<< psubstratepcontact >> +rect 25 9 29 13 +<< nsubstratendiff >> +rect 25 68 29 72 << labels >> rlabel metal1 19 63 19 63 1 wl0 rlabel metal1 19 70 19 70 5 vdd @@ -133,4 +130,6 @@ rlabel metal2 4 7 4 7 2 bl0 rlabel metal2 11 7 11 7 1 bl1 rlabel metal2 43 7 43 7 1 br1 rlabel metal2 50 7 50 7 8 br0 +rlabel polycontact 29 49 29 49 1 Q +rlabel polycontact 25 42 25 42 1 Q_bar << end >> diff --git a/technology/scn4m_subm/mag_lib/dummy_cell_1w_1r.mag b/technology/scn4m_subm/mag_lib/dummy_cell_1w_1r.mag index 03e49f03..9166b42a 100644 --- a/technology/scn4m_subm/mag_lib/dummy_cell_1w_1r.mag +++ b/technology/scn4m_subm/mag_lib/dummy_cell_1w_1r.mag @@ -1,63 +1,10 @@ magic tech scmos -timestamp 1562189027 -<< nwell >> -rect 0 46 54 75 +timestamp 1572949619 << pwell >> rect 0 0 54 46 -<< ntransistor >> -rect 14 33 16 37 -rect 22 29 24 37 -rect 30 29 32 37 -rect 38 33 40 37 -rect 14 17 16 23 -rect 22 17 24 23 -rect 30 17 32 23 -rect 38 17 40 23 -<< ptransistor >> -rect 22 54 24 57 -rect 30 54 32 57 -<< ndiffusion >> -rect 13 33 14 37 -rect 16 33 17 37 -rect 21 33 22 37 -rect 17 29 22 33 -rect 24 29 25 37 -rect 29 29 30 37 -rect 32 33 33 37 -rect 37 33 38 37 -rect 40 33 41 37 -rect 32 29 37 33 -rect 9 21 14 23 -rect 13 17 14 21 -rect 16 17 22 23 -rect 24 17 25 23 -rect 29 17 30 23 -rect 32 17 38 23 -rect 40 21 45 23 -rect 40 17 41 21 -<< pdiffusion >> -rect 21 54 22 57 -rect 24 54 25 57 -rect 29 54 30 57 -rect 32 54 33 57 -<< ndcontact >> -rect 9 33 13 37 -rect 17 33 21 37 -rect 25 29 29 37 -rect 33 33 37 37 -rect 41 33 45 37 -rect 9 17 13 21 -rect 25 17 29 23 -rect 41 17 45 21 -<< pdcontact >> -rect 17 54 21 58 -rect 25 54 29 58 -rect 33 54 37 58 -<< psubstratepcontact >> -rect 25 9 29 13 -<< nsubstratencontact >> -rect 25 68 29 72 +<< nwell >> +rect 0 46 54 75 << polysilicon >> rect 22 57 24 60 rect 30 57 32 60 @@ -79,13 +26,30 @@ rect 14 15 16 17 rect 22 15 24 17 rect 30 15 32 17 rect 38 15 40 17 -<< polycontact >> -rect 27 47 31 51 -rect 10 40 14 44 -rect 23 40 27 44 -rect 40 40 44 44 -rect 12 24 16 28 -rect 38 24 42 28 +<< ndiffusion >> +rect 13 33 14 37 +rect 16 33 17 37 +rect 21 33 22 37 +rect 17 29 22 33 +rect 24 29 25 37 +rect 29 29 30 37 +rect 32 33 33 37 +rect 37 33 38 37 +rect 40 33 41 37 +rect 32 29 37 33 +rect 9 21 14 23 +rect 13 17 14 21 +rect 16 17 22 23 +rect 24 17 25 23 +rect 29 17 30 23 +rect 32 17 38 23 +rect 40 21 45 23 +rect 40 17 41 21 +<< pdiffusion >> +rect 25 57 29 58 +rect 21 54 22 57 +rect 24 54 30 57 +rect 32 54 33 57 << metal1 >> rect 0 68 25 72 rect 29 68 54 72 @@ -107,13 +71,6 @@ rect 29 9 54 13 rect 0 2 16 6 rect 20 2 34 6 rect 38 2 54 6 -<< m2contact >> -rect 25 68 29 72 -rect 25 54 29 58 -rect 16 24 20 28 -rect 34 24 38 28 -rect 16 2 20 6 -rect 34 2 38 6 << metal2 >> rect 2 0 6 72 rect 9 0 13 72 @@ -122,8 +79,48 @@ rect 16 6 20 24 rect 34 6 38 24 rect 41 0 45 72 rect 48 0 52 72 -<< comment >> -rect 0 0 54 70 +<< ntransistor >> +rect 14 33 16 37 +rect 22 29 24 37 +rect 30 29 32 37 +rect 38 33 40 37 +rect 14 17 16 23 +rect 22 17 24 23 +rect 30 17 32 23 +rect 38 17 40 23 +<< ptransistor >> +rect 22 54 24 57 +rect 30 54 32 57 +<< polycontact >> +rect 27 47 31 51 +rect 10 40 14 44 +rect 23 40 27 44 +rect 40 40 44 44 +rect 12 24 16 28 +rect 38 24 42 28 +<< ndcontact >> +rect 9 33 13 37 +rect 17 33 21 37 +rect 25 29 29 37 +rect 33 33 37 37 +rect 41 33 45 37 +rect 9 17 13 21 +rect 25 17 29 23 +rect 41 17 45 21 +<< pdcontact >> +rect 17 54 21 58 +rect 33 54 37 58 +<< m2contact >> +rect 25 68 29 72 +rect 25 54 29 58 +rect 16 24 20 28 +rect 34 24 38 28 +rect 16 2 20 6 +rect 34 2 38 6 +<< psubstratepcontact >> +rect 25 9 29 13 +<< nsubstratendiff >> +rect 25 68 29 72 << labels >> rlabel metal1 19 63 19 63 1 wl0 rlabel metal1 19 70 19 70 5 vdd @@ -133,4 +130,6 @@ rlabel metal2 4 7 4 7 2 bl0 rlabel metal2 11 7 11 7 1 bl1 rlabel metal2 43 7 43 7 1 br1 rlabel metal2 50 7 50 7 8 br0 +rlabel polycontact 29 49 29 49 1 Q +rlabel polycontact 25 42 25 42 1 Q_bar << end >> diff --git a/technology/scn4m_subm/mag_lib/dummy_cell_6t.mag b/technology/scn4m_subm/mag_lib/dummy_cell_6t.mag index 74562f15..7f7591ba 100644 --- a/technology/scn4m_subm/mag_lib/dummy_cell_6t.mag +++ b/technology/scn4m_subm/mag_lib/dummy_cell_6t.mag @@ -1,18 +1,28 @@ magic tech scmos -timestamp 1560809362 -<< nwell >> -rect -8 35 42 57 +timestamp 1572949665 << pwell >> rect -8 -2 42 35 -<< ntransistor >> -rect 7 16 9 24 -rect 29 16 31 24 -rect 10 9 14 11 -rect 24 9 28 11 -<< ptransistor >> -rect 7 43 11 46 -rect 27 43 31 46 +<< nwell >> +rect -8 35 42 57 +<< polysilicon >> +rect 7 46 11 48 +rect 27 46 31 48 +rect 7 41 11 43 +rect 7 27 9 41 +rect 27 40 31 43 +rect 15 39 31 40 +rect 19 38 31 39 +rect 7 26 21 27 +rect 7 25 24 26 +rect 7 24 9 25 +rect 29 24 31 38 +rect 7 14 9 16 +rect 17 11 21 12 +rect 29 14 31 16 +rect -2 9 10 11 +rect 14 9 24 11 +rect 28 9 36 11 << ndiffusion >> rect -2 22 7 24 rect 2 18 7 22 @@ -33,45 +43,6 @@ rect 2 43 7 46 rect 11 43 12 46 rect 26 43 27 46 rect 31 43 32 46 -<< ndcontact >> -rect -2 18 2 22 -rect 10 20 14 24 -rect 24 20 28 24 -rect 32 18 36 22 -rect 10 4 14 8 -rect 24 4 28 8 -<< pdcontact >> -rect -2 42 2 46 -rect 12 42 16 46 -rect 22 42 26 46 -rect 32 42 36 46 -<< psubstratepcontact >> -rect -2 28 2 32 -rect 32 28 36 32 -<< nsubstratencontact >> -rect 32 50 36 54 -<< polysilicon >> -rect 7 46 11 48 -rect 27 46 31 48 -rect 7 41 11 43 -rect 7 27 9 41 -rect 27 40 31 43 -rect 15 39 31 40 -rect 19 38 31 39 -rect 7 26 21 27 -rect 7 25 24 26 -rect 7 24 9 25 -rect 29 24 31 38 -rect 7 14 9 16 -rect 17 11 21 12 -rect 29 14 31 16 -rect -2 9 10 11 -rect 14 9 24 11 -rect 28 9 36 11 -<< polycontact >> -rect 15 35 19 39 -rect 21 26 25 30 -rect 17 12 21 16 << metal1 >> rect -2 50 15 54 rect 19 50 32 54 @@ -92,10 +63,6 @@ rect 32 22 36 28 rect -2 12 17 15 rect 21 12 36 15 rect -2 11 36 12 -<< m2contact >> -rect 15 50 19 54 -rect -2 35 2 39 -rect 32 35 36 39 << metal2 >> rect -2 39 2 54 rect -2 0 2 35 @@ -103,8 +70,39 @@ rect 6 0 10 54 rect 24 0 28 54 rect 32 39 36 54 rect 32 0 36 35 -<< bb >> -rect 0 0 34 52 +<< ntransistor >> +rect 7 16 9 24 +rect 29 16 31 24 +rect 10 9 14 11 +rect 24 9 28 11 +<< ptransistor >> +rect 7 43 11 46 +rect 27 43 31 46 +<< polycontact >> +rect 15 35 19 39 +rect 21 26 25 30 +rect 17 12 21 16 +<< ndcontact >> +rect -2 18 2 22 +rect 10 20 14 24 +rect 24 20 28 24 +rect 32 18 36 22 +rect 10 4 14 8 +rect 24 4 28 8 +<< pdcontact >> +rect -2 42 2 46 +rect 12 42 16 46 +rect 22 42 26 46 +rect 32 42 36 46 +<< m2contact >> +rect 15 50 19 54 +rect -2 35 2 39 +rect 32 35 36 39 +<< psubstratepcontact >> +rect -2 28 2 32 +rect 32 28 36 32 +<< nsubstratencontact >> +rect 32 50 36 54 << labels >> rlabel metal2 0 6 0 6 1 gnd rlabel metal2 34 6 34 6 1 gnd @@ -112,4 +110,6 @@ rlabel m2contact 17 52 17 52 5 vdd rlabel metal2 8 49 8 49 1 bl rlabel metal2 26 49 26 49 1 br rlabel metal1 4 13 4 13 1 wl +rlabel polycontact 17 37 17 37 1 Q +rlabel polycontact 23 28 23 28 1 Q_bar << end >> diff --git a/technology/scn4m_subm/mag_lib/replica_cell_1rw_1r.mag b/technology/scn4m_subm/mag_lib/replica_cell_1rw_1r.mag index f215ff04..9b6e203b 100644 --- a/technology/scn4m_subm/mag_lib/replica_cell_1rw_1r.mag +++ b/technology/scn4m_subm/mag_lib/replica_cell_1rw_1r.mag @@ -1,63 +1,10 @@ magic tech scmos -timestamp 1542221056 -<< nwell >> -rect 0 46 54 75 +timestamp 1572949704 << pwell >> rect 0 0 54 46 -<< ntransistor >> -rect 14 33 16 37 -rect 22 29 24 37 -rect 30 29 32 37 -rect 38 33 40 37 -rect 14 17 16 23 -rect 22 17 24 23 -rect 30 17 32 23 -rect 38 17 40 23 -<< ptransistor >> -rect 22 54 24 57 -rect 30 54 32 57 -<< ndiffusion >> -rect 13 33 14 37 -rect 16 33 17 37 -rect 21 33 22 37 -rect 17 29 22 33 -rect 24 29 25 37 -rect 29 29 30 37 -rect 32 33 33 37 -rect 37 33 38 37 -rect 40 33 41 37 -rect 32 29 37 33 -rect 9 21 14 23 -rect 13 17 14 21 -rect 16 17 22 23 -rect 24 17 25 23 -rect 29 17 30 23 -rect 32 17 38 23 -rect 40 21 45 23 -rect 40 17 41 21 -<< pdiffusion >> -rect 21 54 22 57 -rect 24 54 25 57 -rect 29 54 30 57 -rect 32 54 33 57 -<< ndcontact >> -rect 9 33 13 37 -rect 17 33 21 37 -rect 25 29 29 37 -rect 33 33 37 37 -rect 41 33 45 37 -rect 9 17 13 21 -rect 25 17 29 23 -rect 41 17 45 21 -<< pdcontact >> -rect 17 54 21 58 -rect 25 54 29 58 -rect 33 54 37 58 -<< psubstratepcontact >> -rect 25 9 29 13 -<< nsubstratencontact >> -rect 25 68 29 72 +<< nwell >> +rect 0 46 54 75 << polysilicon >> rect 22 57 24 60 rect 30 57 32 60 @@ -79,13 +26,28 @@ rect 14 15 16 17 rect 22 15 24 17 rect 30 15 32 17 rect 38 15 40 17 -<< polycontact >> -rect 27 47 31 51 -rect 10 40 14 44 -rect 23 40 27 44 -rect 40 40 44 44 -rect 12 24 16 28 -rect 38 24 42 28 +<< ndiffusion >> +rect 13 33 14 37 +rect 16 33 17 37 +rect 21 33 22 37 +rect 17 29 22 33 +rect 24 29 25 37 +rect 29 29 30 37 +rect 32 33 33 37 +rect 37 33 38 37 +rect 40 33 41 37 +rect 32 29 37 33 +rect 9 17 14 23 +rect 16 17 22 23 +rect 24 17 25 23 +rect 29 17 30 23 +rect 32 17 38 23 +rect 40 17 45 23 +<< pdiffusion >> +rect 25 57 29 58 +rect 21 54 22 57 +rect 24 54 30 57 +rect 32 54 33 57 << metal1 >> rect 0 68 25 72 rect 29 68 54 72 @@ -108,17 +70,6 @@ rect 29 9 54 13 rect 0 2 16 6 rect 20 2 34 6 rect 38 2 54 6 -<< m2contact >> -rect 25 68 29 72 -rect 25 54 29 58 -rect 2 33 6 37 -rect 48 33 52 37 -rect 16 24 20 28 -rect 34 24 38 28 -rect 9 17 13 21 -rect 41 17 45 21 -rect 16 2 20 6 -rect 34 2 38 6 << metal2 >> rect 2 37 6 72 rect 2 0 6 33 @@ -131,8 +82,50 @@ rect 41 21 45 72 rect 41 0 45 17 rect 48 37 52 72 rect 48 0 52 33 -<< comment >> -rect 0 0 54 70 +<< ntransistor >> +rect 14 33 16 37 +rect 22 29 24 37 +rect 30 29 32 37 +rect 38 33 40 37 +rect 14 17 16 23 +rect 22 17 24 23 +rect 30 17 32 23 +rect 38 17 40 23 +<< ptransistor >> +rect 22 54 24 57 +rect 30 54 32 57 +<< polycontact >> +rect 27 47 31 51 +rect 10 40 14 44 +rect 23 40 27 44 +rect 40 40 44 44 +rect 12 24 16 28 +rect 38 24 42 28 +<< ndcontact >> +rect 9 33 13 37 +rect 17 33 21 37 +rect 25 29 29 37 +rect 33 33 37 37 +rect 41 33 45 37 +rect 25 17 29 23 +<< pdcontact >> +rect 17 54 21 58 +rect 33 54 37 58 +<< m2contact >> +rect 25 68 29 72 +rect 25 54 29 58 +rect 2 33 6 37 +rect 48 33 52 37 +rect 16 24 20 28 +rect 34 24 38 28 +rect 9 17 13 21 +rect 41 17 45 21 +rect 16 2 20 6 +rect 34 2 38 6 +<< psubstratepcontact >> +rect 25 9 29 13 +<< nsubstratendiff >> +rect 25 68 29 72 << labels >> rlabel metal1 19 63 19 63 1 wl0 rlabel metal1 19 70 19 70 5 vdd @@ -142,4 +135,6 @@ rlabel metal2 4 7 4 7 2 bl0 rlabel metal2 11 7 11 7 1 bl1 rlabel metal2 43 7 43 7 1 br1 rlabel metal2 50 7 50 7 8 br0 +rlabel polycontact 29 49 29 49 1 Q +rlabel polycontact 25 42 25 42 1 Q_bar << end >> diff --git a/technology/scn4m_subm/mag_lib/replica_cell_1w_1r.mag b/technology/scn4m_subm/mag_lib/replica_cell_1w_1r.mag index f215ff04..b2a525e8 100644 --- a/technology/scn4m_subm/mag_lib/replica_cell_1w_1r.mag +++ b/technology/scn4m_subm/mag_lib/replica_cell_1w_1r.mag @@ -1,63 +1,10 @@ magic tech scmos -timestamp 1542221056 -<< nwell >> -rect 0 46 54 75 +timestamp 1572949741 << pwell >> rect 0 0 54 46 -<< ntransistor >> -rect 14 33 16 37 -rect 22 29 24 37 -rect 30 29 32 37 -rect 38 33 40 37 -rect 14 17 16 23 -rect 22 17 24 23 -rect 30 17 32 23 -rect 38 17 40 23 -<< ptransistor >> -rect 22 54 24 57 -rect 30 54 32 57 -<< ndiffusion >> -rect 13 33 14 37 -rect 16 33 17 37 -rect 21 33 22 37 -rect 17 29 22 33 -rect 24 29 25 37 -rect 29 29 30 37 -rect 32 33 33 37 -rect 37 33 38 37 -rect 40 33 41 37 -rect 32 29 37 33 -rect 9 21 14 23 -rect 13 17 14 21 -rect 16 17 22 23 -rect 24 17 25 23 -rect 29 17 30 23 -rect 32 17 38 23 -rect 40 21 45 23 -rect 40 17 41 21 -<< pdiffusion >> -rect 21 54 22 57 -rect 24 54 25 57 -rect 29 54 30 57 -rect 32 54 33 57 -<< ndcontact >> -rect 9 33 13 37 -rect 17 33 21 37 -rect 25 29 29 37 -rect 33 33 37 37 -rect 41 33 45 37 -rect 9 17 13 21 -rect 25 17 29 23 -rect 41 17 45 21 -<< pdcontact >> -rect 17 54 21 58 -rect 25 54 29 58 -rect 33 54 37 58 -<< psubstratepcontact >> -rect 25 9 29 13 -<< nsubstratencontact >> -rect 25 68 29 72 +<< nwell >> +rect 0 46 54 75 << polysilicon >> rect 22 57 24 60 rect 30 57 32 60 @@ -79,13 +26,28 @@ rect 14 15 16 17 rect 22 15 24 17 rect 30 15 32 17 rect 38 15 40 17 -<< polycontact >> -rect 27 47 31 51 -rect 10 40 14 44 -rect 23 40 27 44 -rect 40 40 44 44 -rect 12 24 16 28 -rect 38 24 42 28 +<< ndiffusion >> +rect 13 33 14 37 +rect 16 33 17 37 +rect 21 33 22 37 +rect 17 29 22 33 +rect 24 29 25 37 +rect 29 29 30 37 +rect 32 33 33 37 +rect 37 33 38 37 +rect 40 33 41 37 +rect 32 29 37 33 +rect 9 17 14 23 +rect 16 17 22 23 +rect 24 17 25 23 +rect 29 17 30 23 +rect 32 17 38 23 +rect 40 17 45 23 +<< pdiffusion >> +rect 25 57 29 58 +rect 21 54 22 57 +rect 24 54 30 57 +rect 32 54 33 57 << metal1 >> rect 0 68 25 72 rect 29 68 54 72 @@ -108,17 +70,6 @@ rect 29 9 54 13 rect 0 2 16 6 rect 20 2 34 6 rect 38 2 54 6 -<< m2contact >> -rect 25 68 29 72 -rect 25 54 29 58 -rect 2 33 6 37 -rect 48 33 52 37 -rect 16 24 20 28 -rect 34 24 38 28 -rect 9 17 13 21 -rect 41 17 45 21 -rect 16 2 20 6 -rect 34 2 38 6 << metal2 >> rect 2 37 6 72 rect 2 0 6 33 @@ -131,8 +82,50 @@ rect 41 21 45 72 rect 41 0 45 17 rect 48 37 52 72 rect 48 0 52 33 -<< comment >> -rect 0 0 54 70 +<< ntransistor >> +rect 14 33 16 37 +rect 22 29 24 37 +rect 30 29 32 37 +rect 38 33 40 37 +rect 14 17 16 23 +rect 22 17 24 23 +rect 30 17 32 23 +rect 38 17 40 23 +<< ptransistor >> +rect 22 54 24 57 +rect 30 54 32 57 +<< polycontact >> +rect 27 47 31 51 +rect 10 40 14 44 +rect 23 40 27 44 +rect 40 40 44 44 +rect 12 24 16 28 +rect 38 24 42 28 +<< ndcontact >> +rect 9 33 13 37 +rect 17 33 21 37 +rect 25 29 29 37 +rect 33 33 37 37 +rect 41 33 45 37 +rect 25 17 29 23 +<< pdcontact >> +rect 17 54 21 58 +rect 33 54 37 58 +<< m2contact >> +rect 25 68 29 72 +rect 25 54 29 58 +rect 2 33 6 37 +rect 48 33 52 37 +rect 16 24 20 28 +rect 34 24 38 28 +rect 9 17 13 21 +rect 41 17 45 21 +rect 16 2 20 6 +rect 34 2 38 6 +<< psubstratepcontact >> +rect 25 9 29 13 +<< nsubstratendiff >> +rect 25 68 29 72 << labels >> rlabel metal1 19 63 19 63 1 wl0 rlabel metal1 19 70 19 70 5 vdd @@ -142,4 +135,6 @@ rlabel metal2 4 7 4 7 2 bl0 rlabel metal2 11 7 11 7 1 bl1 rlabel metal2 43 7 43 7 1 br1 rlabel metal2 50 7 50 7 8 br0 +rlabel polycontact 29 49 29 49 1 Q +rlabel polycontact 25 42 25 42 1 Q_bar << end >> diff --git a/technology/scn4m_subm/mag_lib/replica_cell_6t.mag b/technology/scn4m_subm/mag_lib/replica_cell_6t.mag index b5a5f7b8..316082ca 100644 --- a/technology/scn4m_subm/mag_lib/replica_cell_6t.mag +++ b/technology/scn4m_subm/mag_lib/replica_cell_6t.mag @@ -1,18 +1,28 @@ magic tech scmos -timestamp 1560809329 -<< nwell >> -rect -8 35 42 57 +timestamp 1572949776 << pwell >> rect -8 -2 42 35 -<< ntransistor >> -rect 7 16 9 24 -rect 29 16 31 24 -rect 10 9 14 11 -rect 24 9 28 11 -<< ptransistor >> -rect 7 43 11 46 -rect 27 43 31 46 +<< nwell >> +rect -8 35 42 57 +<< polysilicon >> +rect 7 46 11 48 +rect 27 46 31 48 +rect 7 41 11 43 +rect 7 27 9 41 +rect 27 40 31 43 +rect 15 39 31 40 +rect 19 38 31 39 +rect 7 26 21 27 +rect 7 25 24 26 +rect 7 24 9 25 +rect 29 24 31 38 +rect 7 14 9 16 +rect 17 11 21 12 +rect 29 14 31 16 +rect -2 9 10 11 +rect 14 9 24 11 +rect 28 9 36 11 << ndiffusion >> rect -2 22 7 24 rect 2 18 7 22 @@ -33,45 +43,6 @@ rect 2 43 7 46 rect 11 43 12 46 rect 26 43 27 46 rect 31 43 32 46 -<< ndcontact >> -rect -2 18 2 22 -rect 10 20 14 24 -rect 24 20 28 24 -rect 32 18 36 22 -rect 10 4 14 8 -rect 24 4 28 8 -<< pdcontact >> -rect -2 42 2 46 -rect 12 42 16 46 -rect 22 42 26 46 -rect 32 42 36 46 -<< psubstratepcontact >> -rect -2 28 2 32 -rect 32 28 36 32 -<< nsubstratencontact >> -rect 32 50 36 54 -<< polysilicon >> -rect 7 46 11 48 -rect 27 46 31 48 -rect 7 41 11 43 -rect 7 27 9 41 -rect 27 40 31 43 -rect 15 39 31 40 -rect 19 38 31 39 -rect 7 26 21 27 -rect 7 25 24 26 -rect 7 24 9 25 -rect 29 24 31 38 -rect 7 14 9 16 -rect 17 11 21 12 -rect 29 14 31 16 -rect -2 9 10 11 -rect 14 9 24 11 -rect 28 9 36 11 -<< polycontact >> -rect 15 35 19 39 -rect 21 26 25 30 -rect 17 12 21 16 << metal1 >> rect -2 50 15 54 rect 19 50 32 54 @@ -93,12 +64,6 @@ rect 32 22 36 28 rect -2 12 17 15 rect 21 12 36 15 rect -2 11 36 12 -<< m2contact >> -rect 15 50 19 54 -rect -2 35 2 39 -rect 32 35 36 39 -rect 6 4 10 8 -rect 20 4 24 8 << metal2 >> rect -2 39 2 54 rect -2 0 2 35 @@ -107,8 +72,41 @@ rect 6 0 10 4 rect 24 0 28 54 rect 32 39 36 54 rect 32 0 36 35 -<< bb >> -rect 0 0 34 52 +<< ntransistor >> +rect 7 16 9 24 +rect 29 16 31 24 +rect 10 9 14 11 +rect 24 9 28 11 +<< ptransistor >> +rect 7 43 11 46 +rect 27 43 31 46 +<< polycontact >> +rect 15 35 19 39 +rect 21 26 25 30 +rect 17 12 21 16 +<< ndcontact >> +rect -2 18 2 22 +rect 10 20 14 24 +rect 24 20 28 24 +rect 32 18 36 22 +rect 10 4 14 8 +rect 24 4 28 8 +<< pdcontact >> +rect -2 42 2 46 +rect 12 42 16 46 +rect 22 42 26 46 +rect 32 42 36 46 +<< m2contact >> +rect 15 50 19 54 +rect -2 35 2 39 +rect 32 35 36 39 +rect 6 4 10 8 +rect 20 4 24 8 +<< psubstratepcontact >> +rect -2 28 2 32 +rect 32 28 36 32 +<< nsubstratencontact >> +rect 32 50 36 54 << labels >> rlabel metal2 0 6 0 6 1 gnd rlabel metal2 34 6 34 6 1 gnd @@ -116,4 +114,6 @@ rlabel m2contact 17 52 17 52 5 vdd rlabel metal2 8 49 8 49 1 bl rlabel metal2 26 49 26 49 1 br rlabel metal1 4 13 4 13 1 wl +rlabel polycontact 17 37 17 37 1 Q +rlabel polycontact 23 28 23 28 1 Q_bar << end >> From 88d3da0b4aadf1be35af4d07fa5875ea49a71af9 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Wed, 18 Dec 2019 12:45:12 +0000 Subject: [PATCH 02/31] fix control logic pex labels with multiport --- compiler/sram/sram_base.py | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index 547ba517..cd9fb19d 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -112,11 +112,13 @@ class sram_base(design, verilog, lef): # add pex labels for control logic for i in range (0,len(self.control_logic_insts)): - control_logic_offset = self.control_logic_insts[i].offset - for output in self.control_logic_insts[i].mod.output_list: - pin = self.control_logic_insts[i].mod.get_pin(output) - offset = [control_logic_offset[0] + pin.center()[0], control_logic_offset[1] + pin.center()[1]] - self.add_layout_pin_rect_center("{0}{1}".format(pin.name,i), "metal1", offset) + instance = self.control_logic_insts[i] + control_logic_offset = instance.offset + for output in instance.mod.output_list: + pin = instance.mod.get_pin(output) + pin.transform([0,0], instance.mirror, instance.rotate) + offset = [control_logic_offset[0] + pin.center()[0], control_logic_offset[1] + pin.center()[1]] + self.add_layout_pin_rect_center("{0}{1}".format(pin.name,i), "metal1", offset) From 5b44dce50d37e4ef30e2d3115536208dc700ae29 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Mon, 23 Dec 2019 02:22:11 +0000 Subject: [PATCH 03/31] added labels to scn4m magic libaries --- technology/scn4m_subm/mag_lib/cell_1rw_1r.mag | 141 +++++++++-------- technology/scn4m_subm/mag_lib/cell_1w_1r.mag | 141 +++++++++-------- technology/scn4m_subm/mag_lib/cell_6t.mag | 116 +++++++------- .../scn4m_subm/mag_lib/dummy_cell_1rw_1r.mag | 141 ++++++++--------- .../scn4m_subm/mag_lib/dummy_cell_1w_1r.mag | 141 ++++++++--------- .../scn4m_subm/mag_lib/dummy_cell_6t.mag | 110 ++++++------- .../mag_lib/replica_cell_1rw_1r.mag | 145 +++++++++--------- .../scn4m_subm/mag_lib/replica_cell_1w_1r.mag | 145 +++++++++--------- .../scn4m_subm/mag_lib/replica_cell_6t.mag | 114 +++++++------- 9 files changed, 621 insertions(+), 573 deletions(-) diff --git a/technology/scn4m_subm/mag_lib/cell_1rw_1r.mag b/technology/scn4m_subm/mag_lib/cell_1rw_1r.mag index 0f2cdadb..0484df70 100644 --- a/technology/scn4m_subm/mag_lib/cell_1rw_1r.mag +++ b/technology/scn4m_subm/mag_lib/cell_1rw_1r.mag @@ -1,31 +1,22 @@ magic tech scmos -timestamp 1572948731 -<< pwell >> -rect 0 0 54 46 +timestamp 1577066542 << nwell >> rect 0 46 54 75 -<< polysilicon >> -rect 22 57 24 60 -rect 30 57 32 60 -rect 22 44 24 54 -rect 30 51 32 54 -rect 31 47 32 51 -rect 14 37 16 44 -rect 22 40 23 44 -rect 22 37 24 40 -rect 30 37 32 47 -rect 38 37 40 44 -rect 14 31 16 33 -rect 38 31 40 33 -rect 14 23 16 24 -rect 22 23 24 29 -rect 30 23 32 29 -rect 38 23 40 24 -rect 14 15 16 17 -rect 22 15 24 17 -rect 30 15 32 17 -rect 38 15 40 17 +<< pwell >> +rect 0 0 54 46 +<< ntransistor >> +rect 14 33 16 37 +rect 22 29 24 37 +rect 30 29 32 37 +rect 38 33 40 37 +rect 14 17 16 23 +rect 22 17 24 23 +rect 30 17 32 23 +rect 38 17 40 23 +<< ptransistor >> +rect 22 54 24 57 +rect 30 54 32 57 << ndiffusion >> rect 13 33 14 37 rect 16 33 17 37 @@ -50,6 +41,51 @@ rect 21 54 22 57 rect 24 54 25 57 rect 29 54 30 57 rect 32 54 33 57 +<< ndcontact >> +rect 9 33 13 37 +rect 17 33 21 37 +rect 25 29 29 37 +rect 33 33 37 37 +rect 41 33 45 37 +rect 9 17 13 21 +rect 25 17 29 23 +rect 41 17 45 21 +<< pdcontact >> +rect 17 54 21 58 +rect 25 54 29 58 +rect 33 54 37 58 +<< psubstratepcontact >> +rect 25 9 29 13 +<< nsubstratencontact >> +rect 25 68 29 72 +<< polysilicon >> +rect 22 57 24 60 +rect 30 57 32 60 +rect 22 44 24 54 +rect 30 51 32 54 +rect 31 47 32 51 +rect 14 37 16 44 +rect 22 40 23 44 +rect 22 37 24 40 +rect 30 37 32 47 +rect 38 37 40 44 +rect 14 31 16 33 +rect 38 31 40 33 +rect 14 23 16 24 +rect 22 23 24 29 +rect 30 23 32 29 +rect 38 23 40 24 +rect 14 15 16 17 +rect 22 15 24 17 +rect 30 15 32 17 +rect 38 15 40 17 +<< polycontact >> +rect 27 47 31 51 +rect 10 40 14 44 +rect 23 40 27 44 +rect 40 40 44 44 +rect 12 24 16 28 +rect 38 24 42 28 << metal1 >> rect 0 68 25 72 rect 29 68 54 72 @@ -71,6 +107,17 @@ rect 29 9 54 13 rect 0 2 16 6 rect 20 2 34 6 rect 38 2 54 6 +<< m2contact >> +rect 25 68 29 72 +rect 25 54 29 58 +rect 2 33 6 37 +rect 48 33 52 37 +rect 16 24 20 28 +rect 34 24 38 28 +rect 9 17 13 21 +rect 41 17 45 21 +rect 16 2 20 6 +rect 34 2 38 6 << metal2 >> rect 2 37 6 72 rect 2 0 6 33 @@ -80,47 +127,11 @@ rect 9 0 13 17 rect 16 6 20 24 rect 34 6 38 24 rect 41 21 45 72 -rect 48 37 52 72 rect 41 0 45 17 +rect 48 37 52 72 rect 48 0 52 33 -<< ntransistor >> -rect 14 33 16 37 -rect 22 29 24 37 -rect 30 29 32 37 -rect 38 33 40 37 -rect 14 17 16 23 -rect 22 17 24 23 -rect 30 17 32 23 -rect 38 17 40 23 -<< ptransistor >> -rect 22 54 24 57 -rect 30 54 32 57 -<< polycontact >> -rect 27 47 31 51 -rect 10 40 14 44 -rect 23 40 27 44 -rect 40 40 44 44 -rect 12 24 16 28 -rect 38 24 42 28 -<< ndcontact >> -rect 9 33 13 37 -rect 17 33 21 37 -rect 25 29 29 37 -rect 33 33 37 37 -rect 41 33 45 37 -rect 25 17 29 23 -<< pdcontact >> -rect 17 54 21 58 -rect 33 54 37 58 -<< m2contact >> -rect 2 33 6 37 -rect 48 33 52 37 -rect 16 24 20 28 -rect 34 24 38 28 -rect 16 2 20 6 -rect 34 2 38 6 -<< psubstratepcontact >> -rect 25 9 29 13 +<< comment >> +rect 0 0 54 70 << labels >> rlabel metal1 19 63 19 63 1 wl0 rlabel metal1 19 70 19 70 5 vdd @@ -130,6 +141,6 @@ rlabel metal2 4 7 4 7 2 bl0 rlabel metal2 11 7 11 7 1 bl1 rlabel metal2 43 7 43 7 1 br1 rlabel metal2 50 7 50 7 8 br0 -rlabel metal1 19 49 19 49 1 Q -rlabel metal1 35 42 35 42 1 Q_bar +rlabel polycontact 29 49 29 49 1 Q +rlabel polycontact 25 42 25 42 1 Q_bar << end >> diff --git a/technology/scn4m_subm/mag_lib/cell_1w_1r.mag b/technology/scn4m_subm/mag_lib/cell_1w_1r.mag index 91d06069..71a3b1bc 100644 --- a/technology/scn4m_subm/mag_lib/cell_1w_1r.mag +++ b/technology/scn4m_subm/mag_lib/cell_1w_1r.mag @@ -1,31 +1,22 @@ magic tech scmos -timestamp 1572948787 -<< pwell >> -rect 0 0 54 46 +timestamp 1577067400 << nwell >> rect 0 46 54 75 -<< polysilicon >> -rect 22 57 24 60 -rect 30 57 32 60 -rect 22 44 24 54 -rect 30 51 32 54 -rect 31 47 32 51 -rect 14 37 16 44 -rect 22 40 23 44 -rect 22 37 24 40 -rect 30 37 32 47 -rect 38 37 40 44 -rect 14 31 16 33 -rect 38 31 40 33 -rect 14 23 16 24 -rect 22 23 24 29 -rect 30 23 32 29 -rect 38 23 40 24 -rect 14 15 16 17 -rect 22 15 24 17 -rect 30 15 32 17 -rect 38 15 40 17 +<< pwell >> +rect 0 0 54 46 +<< ntransistor >> +rect 14 33 16 37 +rect 22 29 24 37 +rect 30 29 32 37 +rect 38 33 40 37 +rect 14 17 16 23 +rect 22 17 24 23 +rect 30 17 32 23 +rect 38 17 40 23 +<< ptransistor >> +rect 22 54 24 57 +rect 30 54 32 57 << ndiffusion >> rect 13 33 14 37 rect 16 33 17 37 @@ -50,6 +41,51 @@ rect 21 54 22 57 rect 24 54 25 57 rect 29 54 30 57 rect 32 54 33 57 +<< ndcontact >> +rect 9 33 13 37 +rect 17 33 21 37 +rect 25 29 29 37 +rect 33 33 37 37 +rect 41 33 45 37 +rect 9 17 13 21 +rect 25 17 29 23 +rect 41 17 45 21 +<< pdcontact >> +rect 17 54 21 58 +rect 25 54 29 58 +rect 33 54 37 58 +<< psubstratepcontact >> +rect 25 9 29 13 +<< nsubstratencontact >> +rect 25 68 29 72 +<< polysilicon >> +rect 22 57 24 60 +rect 30 57 32 60 +rect 22 44 24 54 +rect 30 51 32 54 +rect 31 47 32 51 +rect 14 37 16 44 +rect 22 40 23 44 +rect 22 37 24 40 +rect 30 37 32 47 +rect 38 37 40 44 +rect 14 31 16 33 +rect 38 31 40 33 +rect 14 23 16 24 +rect 22 23 24 29 +rect 30 23 32 29 +rect 38 23 40 24 +rect 14 15 16 17 +rect 22 15 24 17 +rect 30 15 32 17 +rect 38 15 40 17 +<< polycontact >> +rect 27 47 31 51 +rect 10 40 14 44 +rect 23 40 27 44 +rect 40 40 44 44 +rect 12 24 16 28 +rect 38 24 42 28 << metal1 >> rect 0 68 25 72 rect 29 68 54 72 @@ -71,6 +107,17 @@ rect 29 9 54 13 rect 0 2 16 6 rect 20 2 34 6 rect 38 2 54 6 +<< m2contact >> +rect 25 68 29 72 +rect 25 54 29 58 +rect 2 33 6 37 +rect 48 33 52 37 +rect 16 24 20 28 +rect 34 24 38 28 +rect 9 17 13 21 +rect 41 17 45 21 +rect 16 2 20 6 +rect 34 2 38 6 << metal2 >> rect 2 37 6 72 rect 2 0 6 33 @@ -80,47 +127,11 @@ rect 9 0 13 17 rect 16 6 20 24 rect 34 6 38 24 rect 41 21 45 72 -rect 48 37 52 72 rect 41 0 45 17 +rect 48 37 52 72 rect 48 0 52 33 -<< ntransistor >> -rect 14 33 16 37 -rect 22 29 24 37 -rect 30 29 32 37 -rect 38 33 40 37 -rect 14 17 16 23 -rect 22 17 24 23 -rect 30 17 32 23 -rect 38 17 40 23 -<< ptransistor >> -rect 22 54 24 57 -rect 30 54 32 57 -<< polycontact >> -rect 27 47 31 51 -rect 10 40 14 44 -rect 23 40 27 44 -rect 40 40 44 44 -rect 12 24 16 28 -rect 38 24 42 28 -<< ndcontact >> -rect 9 33 13 37 -rect 17 33 21 37 -rect 25 29 29 37 -rect 33 33 37 37 -rect 41 33 45 37 -rect 25 17 29 23 -<< pdcontact >> -rect 17 54 21 58 -rect 33 54 37 58 -<< m2contact >> -rect 2 33 6 37 -rect 48 33 52 37 -rect 16 24 20 28 -rect 34 24 38 28 -rect 16 2 20 6 -rect 34 2 38 6 -<< psubstratepcontact >> -rect 25 9 29 13 +<< comment >> +rect 0 0 54 70 << labels >> rlabel metal1 19 63 19 63 1 wl0 rlabel metal1 19 70 19 70 5 vdd @@ -130,6 +141,6 @@ rlabel metal2 4 7 4 7 2 bl0 rlabel metal2 11 7 11 7 1 bl1 rlabel metal2 43 7 43 7 1 br1 rlabel metal2 50 7 50 7 8 br0 -rlabel metal1 19 49 19 49 1 Q -rlabel metal1 35 42 35 42 1 Q_bar +rlabel polycontact 29 49 29 49 1 Q +rlabel polycontact 25 42 25 42 1 Q_bar << end >> diff --git a/technology/scn4m_subm/mag_lib/cell_6t.mag b/technology/scn4m_subm/mag_lib/cell_6t.mag index 6b277af2..17206ac6 100644 --- a/technology/scn4m_subm/mag_lib/cell_6t.mag +++ b/technology/scn4m_subm/mag_lib/cell_6t.mag @@ -1,28 +1,18 @@ magic tech scmos -timestamp 1572949512 -<< pwell >> -rect -8 -2 42 35 +timestamp 1577066121 << nwell >> rect -8 35 42 57 -<< polysilicon >> -rect 7 46 11 48 -rect 27 46 31 48 -rect 7 41 11 43 -rect 7 27 9 41 -rect 27 40 31 43 -rect 15 39 31 40 -rect 19 38 31 39 -rect 7 26 21 27 -rect 7 25 24 26 -rect 7 24 9 25 -rect 29 24 31 38 -rect 7 14 9 16 -rect 17 11 21 12 -rect 29 14 31 16 -rect -2 9 10 11 -rect 14 9 24 11 -rect 28 9 36 11 +<< pwell >> +rect -8 -2 42 35 +<< ntransistor >> +rect 7 16 9 24 +rect 29 16 31 24 +rect 10 9 14 11 +rect 24 9 28 11 +<< ptransistor >> +rect 7 43 11 46 +rect 27 43 31 46 << ndiffusion >> rect -2 22 7 24 rect 2 18 7 22 @@ -43,6 +33,45 @@ rect 2 43 7 46 rect 11 43 12 46 rect 26 43 27 46 rect 31 43 32 46 +<< ndcontact >> +rect -2 18 2 22 +rect 10 20 14 24 +rect 24 20 28 24 +rect 32 18 36 22 +rect 10 4 14 8 +rect 24 4 28 8 +<< pdcontact >> +rect -2 42 2 46 +rect 12 42 16 46 +rect 22 42 26 46 +rect 32 42 36 46 +<< psubstratepcontact >> +rect -2 28 2 32 +rect 32 28 36 32 +<< nsubstratencontact >> +rect 32 50 36 54 +<< polysilicon >> +rect 7 46 11 48 +rect 27 46 31 48 +rect 7 41 11 43 +rect 7 27 9 41 +rect 27 40 31 43 +rect 15 39 31 40 +rect 19 38 31 39 +rect 7 26 21 27 +rect 7 25 24 26 +rect 7 24 9 25 +rect 29 24 31 38 +rect 7 14 9 16 +rect 17 11 21 12 +rect 29 14 31 16 +rect -2 9 10 11 +rect 14 9 24 11 +rect 28 9 36 11 +<< polycontact >> +rect 15 35 19 39 +rect 21 26 25 30 +rect 17 12 21 16 << metal1 >> rect -2 50 15 54 rect 19 50 32 54 @@ -63,6 +92,12 @@ rect 32 22 36 28 rect -2 12 17 15 rect 21 12 36 15 rect -2 11 36 12 +<< m2contact >> +rect 15 50 19 54 +rect -2 35 2 39 +rect 32 35 36 39 +rect 6 4 10 8 +rect 20 4 24 8 << metal2 >> rect -2 39 2 54 rect -2 0 2 35 @@ -71,41 +106,8 @@ rect 6 0 10 4 rect 24 0 28 54 rect 32 39 36 54 rect 32 0 36 35 -<< ntransistor >> -rect 7 16 9 24 -rect 29 16 31 24 -rect 10 9 14 11 -rect 24 9 28 11 -<< ptransistor >> -rect 7 43 11 46 -rect 27 43 31 46 -<< polycontact >> -rect 15 35 19 39 -rect 21 26 25 30 -rect 17 12 21 16 -<< ndcontact >> -rect -2 18 2 22 -rect 10 20 14 24 -rect 24 20 28 24 -rect 32 18 36 22 -rect 10 4 14 8 -rect 24 4 28 8 -<< pdcontact >> -rect -2 42 2 46 -rect 12 42 16 46 -rect 22 42 26 46 -rect 32 42 36 46 -<< m2contact >> -rect 15 50 19 54 -rect -2 35 2 39 -rect 32 35 36 39 -rect 6 4 10 8 -rect 20 4 24 8 -<< psubstratepcontact >> -rect -2 28 2 32 -rect 32 28 36 32 -<< nsubstratencontact >> -rect 32 50 36 54 +<< bb >> +rect 0 0 34 52 << labels >> rlabel metal2 0 6 0 6 1 gnd rlabel metal2 34 6 34 6 1 gnd @@ -113,6 +115,6 @@ rlabel m2contact 17 52 17 52 5 vdd rlabel metal2 8 49 8 49 1 bl rlabel metal2 26 49 26 49 1 br rlabel metal1 4 13 4 13 1 wl -rlabel polycontact 23 28 23 28 1 Q_bar rlabel polycontact 17 37 17 37 1 Q +rlabel polycontact 23 28 23 28 1 Q_bar << end >> diff --git a/technology/scn4m_subm/mag_lib/dummy_cell_1rw_1r.mag b/technology/scn4m_subm/mag_lib/dummy_cell_1rw_1r.mag index 79b5daf0..1931485f 100644 --- a/technology/scn4m_subm/mag_lib/dummy_cell_1rw_1r.mag +++ b/technology/scn4m_subm/mag_lib/dummy_cell_1rw_1r.mag @@ -1,10 +1,63 @@ magic tech scmos -timestamp 1572949567 -<< pwell >> -rect 0 0 54 46 +timestamp 1577067400 << nwell >> rect 0 46 54 75 +<< pwell >> +rect 0 0 54 46 +<< ntransistor >> +rect 14 33 16 37 +rect 22 29 24 37 +rect 30 29 32 37 +rect 38 33 40 37 +rect 14 17 16 23 +rect 22 17 24 23 +rect 30 17 32 23 +rect 38 17 40 23 +<< ptransistor >> +rect 22 54 24 57 +rect 30 54 32 57 +<< ndiffusion >> +rect 13 33 14 37 +rect 16 33 17 37 +rect 21 33 22 37 +rect 17 29 22 33 +rect 24 29 25 37 +rect 29 29 30 37 +rect 32 33 33 37 +rect 37 33 38 37 +rect 40 33 41 37 +rect 32 29 37 33 +rect 9 21 14 23 +rect 13 17 14 21 +rect 16 17 22 23 +rect 24 17 25 23 +rect 29 17 30 23 +rect 32 17 38 23 +rect 40 21 45 23 +rect 40 17 41 21 +<< pdiffusion >> +rect 21 54 22 57 +rect 24 54 25 57 +rect 29 54 30 57 +rect 32 54 33 57 +<< ndcontact >> +rect 9 33 13 37 +rect 17 33 21 37 +rect 25 29 29 37 +rect 33 33 37 37 +rect 41 33 45 37 +rect 9 17 13 21 +rect 25 17 29 23 +rect 41 17 45 21 +<< pdcontact >> +rect 17 54 21 58 +rect 25 54 29 58 +rect 33 54 37 58 +<< psubstratepcontact >> +rect 25 9 29 13 +<< nsubstratencontact >> +rect 25 68 29 72 << polysilicon >> rect 22 57 24 60 rect 30 57 32 60 @@ -26,30 +79,13 @@ rect 14 15 16 17 rect 22 15 24 17 rect 30 15 32 17 rect 38 15 40 17 -<< ndiffusion >> -rect 13 33 14 37 -rect 16 33 17 37 -rect 21 33 22 37 -rect 17 29 22 33 -rect 24 29 25 37 -rect 29 29 30 37 -rect 32 33 33 37 -rect 37 33 38 37 -rect 40 33 41 37 -rect 32 29 37 33 -rect 9 21 14 23 -rect 13 17 14 21 -rect 16 17 22 23 -rect 24 17 25 23 -rect 29 17 30 23 -rect 32 17 38 23 -rect 40 21 45 23 -rect 40 17 41 21 -<< pdiffusion >> -rect 25 57 29 58 -rect 21 54 22 57 -rect 24 54 30 57 -rect 32 54 33 57 +<< polycontact >> +rect 27 47 31 51 +rect 10 40 14 44 +rect 23 40 27 44 +rect 40 40 44 44 +rect 12 24 16 28 +rect 38 24 42 28 << metal1 >> rect 0 68 25 72 rect 29 68 54 72 @@ -71,6 +107,13 @@ rect 29 9 54 13 rect 0 2 16 6 rect 20 2 34 6 rect 38 2 54 6 +<< m2contact >> +rect 25 68 29 72 +rect 25 54 29 58 +rect 16 24 20 28 +rect 34 24 38 28 +rect 16 2 20 6 +rect 34 2 38 6 << metal2 >> rect 2 0 6 72 rect 9 0 13 72 @@ -79,48 +122,8 @@ rect 16 6 20 24 rect 34 6 38 24 rect 41 0 45 72 rect 48 0 52 72 -<< ntransistor >> -rect 14 33 16 37 -rect 22 29 24 37 -rect 30 29 32 37 -rect 38 33 40 37 -rect 14 17 16 23 -rect 22 17 24 23 -rect 30 17 32 23 -rect 38 17 40 23 -<< ptransistor >> -rect 22 54 24 57 -rect 30 54 32 57 -<< polycontact >> -rect 27 47 31 51 -rect 10 40 14 44 -rect 23 40 27 44 -rect 40 40 44 44 -rect 12 24 16 28 -rect 38 24 42 28 -<< ndcontact >> -rect 9 33 13 37 -rect 17 33 21 37 -rect 25 29 29 37 -rect 33 33 37 37 -rect 41 33 45 37 -rect 9 17 13 21 -rect 25 17 29 23 -rect 41 17 45 21 -<< pdcontact >> -rect 17 54 21 58 -rect 33 54 37 58 -<< m2contact >> -rect 25 68 29 72 -rect 25 54 29 58 -rect 16 24 20 28 -rect 34 24 38 28 -rect 16 2 20 6 -rect 34 2 38 6 -<< psubstratepcontact >> -rect 25 9 29 13 -<< nsubstratendiff >> -rect 25 68 29 72 +<< comment >> +rect 0 0 54 70 << labels >> rlabel metal1 19 63 19 63 1 wl0 rlabel metal1 19 70 19 70 5 vdd diff --git a/technology/scn4m_subm/mag_lib/dummy_cell_1w_1r.mag b/technology/scn4m_subm/mag_lib/dummy_cell_1w_1r.mag index 9166b42a..1931485f 100644 --- a/technology/scn4m_subm/mag_lib/dummy_cell_1w_1r.mag +++ b/technology/scn4m_subm/mag_lib/dummy_cell_1w_1r.mag @@ -1,10 +1,63 @@ magic tech scmos -timestamp 1572949619 -<< pwell >> -rect 0 0 54 46 +timestamp 1577067400 << nwell >> rect 0 46 54 75 +<< pwell >> +rect 0 0 54 46 +<< ntransistor >> +rect 14 33 16 37 +rect 22 29 24 37 +rect 30 29 32 37 +rect 38 33 40 37 +rect 14 17 16 23 +rect 22 17 24 23 +rect 30 17 32 23 +rect 38 17 40 23 +<< ptransistor >> +rect 22 54 24 57 +rect 30 54 32 57 +<< ndiffusion >> +rect 13 33 14 37 +rect 16 33 17 37 +rect 21 33 22 37 +rect 17 29 22 33 +rect 24 29 25 37 +rect 29 29 30 37 +rect 32 33 33 37 +rect 37 33 38 37 +rect 40 33 41 37 +rect 32 29 37 33 +rect 9 21 14 23 +rect 13 17 14 21 +rect 16 17 22 23 +rect 24 17 25 23 +rect 29 17 30 23 +rect 32 17 38 23 +rect 40 21 45 23 +rect 40 17 41 21 +<< pdiffusion >> +rect 21 54 22 57 +rect 24 54 25 57 +rect 29 54 30 57 +rect 32 54 33 57 +<< ndcontact >> +rect 9 33 13 37 +rect 17 33 21 37 +rect 25 29 29 37 +rect 33 33 37 37 +rect 41 33 45 37 +rect 9 17 13 21 +rect 25 17 29 23 +rect 41 17 45 21 +<< pdcontact >> +rect 17 54 21 58 +rect 25 54 29 58 +rect 33 54 37 58 +<< psubstratepcontact >> +rect 25 9 29 13 +<< nsubstratencontact >> +rect 25 68 29 72 << polysilicon >> rect 22 57 24 60 rect 30 57 32 60 @@ -26,30 +79,13 @@ rect 14 15 16 17 rect 22 15 24 17 rect 30 15 32 17 rect 38 15 40 17 -<< ndiffusion >> -rect 13 33 14 37 -rect 16 33 17 37 -rect 21 33 22 37 -rect 17 29 22 33 -rect 24 29 25 37 -rect 29 29 30 37 -rect 32 33 33 37 -rect 37 33 38 37 -rect 40 33 41 37 -rect 32 29 37 33 -rect 9 21 14 23 -rect 13 17 14 21 -rect 16 17 22 23 -rect 24 17 25 23 -rect 29 17 30 23 -rect 32 17 38 23 -rect 40 21 45 23 -rect 40 17 41 21 -<< pdiffusion >> -rect 25 57 29 58 -rect 21 54 22 57 -rect 24 54 30 57 -rect 32 54 33 57 +<< polycontact >> +rect 27 47 31 51 +rect 10 40 14 44 +rect 23 40 27 44 +rect 40 40 44 44 +rect 12 24 16 28 +rect 38 24 42 28 << metal1 >> rect 0 68 25 72 rect 29 68 54 72 @@ -71,6 +107,13 @@ rect 29 9 54 13 rect 0 2 16 6 rect 20 2 34 6 rect 38 2 54 6 +<< m2contact >> +rect 25 68 29 72 +rect 25 54 29 58 +rect 16 24 20 28 +rect 34 24 38 28 +rect 16 2 20 6 +rect 34 2 38 6 << metal2 >> rect 2 0 6 72 rect 9 0 13 72 @@ -79,48 +122,8 @@ rect 16 6 20 24 rect 34 6 38 24 rect 41 0 45 72 rect 48 0 52 72 -<< ntransistor >> -rect 14 33 16 37 -rect 22 29 24 37 -rect 30 29 32 37 -rect 38 33 40 37 -rect 14 17 16 23 -rect 22 17 24 23 -rect 30 17 32 23 -rect 38 17 40 23 -<< ptransistor >> -rect 22 54 24 57 -rect 30 54 32 57 -<< polycontact >> -rect 27 47 31 51 -rect 10 40 14 44 -rect 23 40 27 44 -rect 40 40 44 44 -rect 12 24 16 28 -rect 38 24 42 28 -<< ndcontact >> -rect 9 33 13 37 -rect 17 33 21 37 -rect 25 29 29 37 -rect 33 33 37 37 -rect 41 33 45 37 -rect 9 17 13 21 -rect 25 17 29 23 -rect 41 17 45 21 -<< pdcontact >> -rect 17 54 21 58 -rect 33 54 37 58 -<< m2contact >> -rect 25 68 29 72 -rect 25 54 29 58 -rect 16 24 20 28 -rect 34 24 38 28 -rect 16 2 20 6 -rect 34 2 38 6 -<< psubstratepcontact >> -rect 25 9 29 13 -<< nsubstratendiff >> -rect 25 68 29 72 +<< comment >> +rect 0 0 54 70 << labels >> rlabel metal1 19 63 19 63 1 wl0 rlabel metal1 19 70 19 70 5 vdd diff --git a/technology/scn4m_subm/mag_lib/dummy_cell_6t.mag b/technology/scn4m_subm/mag_lib/dummy_cell_6t.mag index 7f7591ba..515ef682 100644 --- a/technology/scn4m_subm/mag_lib/dummy_cell_6t.mag +++ b/technology/scn4m_subm/mag_lib/dummy_cell_6t.mag @@ -1,28 +1,18 @@ magic tech scmos -timestamp 1572949665 -<< pwell >> -rect -8 -2 42 35 +timestamp 1577067400 << nwell >> rect -8 35 42 57 -<< polysilicon >> -rect 7 46 11 48 -rect 27 46 31 48 -rect 7 41 11 43 -rect 7 27 9 41 -rect 27 40 31 43 -rect 15 39 31 40 -rect 19 38 31 39 -rect 7 26 21 27 -rect 7 25 24 26 -rect 7 24 9 25 -rect 29 24 31 38 -rect 7 14 9 16 -rect 17 11 21 12 -rect 29 14 31 16 -rect -2 9 10 11 -rect 14 9 24 11 -rect 28 9 36 11 +<< pwell >> +rect -8 -2 42 35 +<< ntransistor >> +rect 7 16 9 24 +rect 29 16 31 24 +rect 10 9 14 11 +rect 24 9 28 11 +<< ptransistor >> +rect 7 43 11 46 +rect 27 43 31 46 << ndiffusion >> rect -2 22 7 24 rect 2 18 7 22 @@ -43,6 +33,45 @@ rect 2 43 7 46 rect 11 43 12 46 rect 26 43 27 46 rect 31 43 32 46 +<< ndcontact >> +rect -2 18 2 22 +rect 10 20 14 24 +rect 24 20 28 24 +rect 32 18 36 22 +rect 10 4 14 8 +rect 24 4 28 8 +<< pdcontact >> +rect -2 42 2 46 +rect 12 42 16 46 +rect 22 42 26 46 +rect 32 42 36 46 +<< psubstratepcontact >> +rect -2 28 2 32 +rect 32 28 36 32 +<< nsubstratencontact >> +rect 32 50 36 54 +<< polysilicon >> +rect 7 46 11 48 +rect 27 46 31 48 +rect 7 41 11 43 +rect 7 27 9 41 +rect 27 40 31 43 +rect 15 39 31 40 +rect 19 38 31 39 +rect 7 26 21 27 +rect 7 25 24 26 +rect 7 24 9 25 +rect 29 24 31 38 +rect 7 14 9 16 +rect 17 11 21 12 +rect 29 14 31 16 +rect -2 9 10 11 +rect 14 9 24 11 +rect 28 9 36 11 +<< polycontact >> +rect 15 35 19 39 +rect 21 26 25 30 +rect 17 12 21 16 << metal1 >> rect -2 50 15 54 rect 19 50 32 54 @@ -63,6 +92,10 @@ rect 32 22 36 28 rect -2 12 17 15 rect 21 12 36 15 rect -2 11 36 12 +<< m2contact >> +rect 15 50 19 54 +rect -2 35 2 39 +rect 32 35 36 39 << metal2 >> rect -2 39 2 54 rect -2 0 2 35 @@ -70,39 +103,8 @@ rect 6 0 10 54 rect 24 0 28 54 rect 32 39 36 54 rect 32 0 36 35 -<< ntransistor >> -rect 7 16 9 24 -rect 29 16 31 24 -rect 10 9 14 11 -rect 24 9 28 11 -<< ptransistor >> -rect 7 43 11 46 -rect 27 43 31 46 -<< polycontact >> -rect 15 35 19 39 -rect 21 26 25 30 -rect 17 12 21 16 -<< ndcontact >> -rect -2 18 2 22 -rect 10 20 14 24 -rect 24 20 28 24 -rect 32 18 36 22 -rect 10 4 14 8 -rect 24 4 28 8 -<< pdcontact >> -rect -2 42 2 46 -rect 12 42 16 46 -rect 22 42 26 46 -rect 32 42 36 46 -<< m2contact >> -rect 15 50 19 54 -rect -2 35 2 39 -rect 32 35 36 39 -<< psubstratepcontact >> -rect -2 28 2 32 -rect 32 28 36 32 -<< nsubstratencontact >> -rect 32 50 36 54 +<< bb >> +rect 0 0 34 52 << labels >> rlabel metal2 0 6 0 6 1 gnd rlabel metal2 34 6 34 6 1 gnd diff --git a/technology/scn4m_subm/mag_lib/replica_cell_1rw_1r.mag b/technology/scn4m_subm/mag_lib/replica_cell_1rw_1r.mag index 9b6e203b..982e1630 100644 --- a/technology/scn4m_subm/mag_lib/replica_cell_1rw_1r.mag +++ b/technology/scn4m_subm/mag_lib/replica_cell_1rw_1r.mag @@ -1,10 +1,63 @@ magic tech scmos -timestamp 1572949704 -<< pwell >> -rect 0 0 54 46 +timestamp 1577067400 << nwell >> rect 0 46 54 75 +<< pwell >> +rect 0 0 54 46 +<< ntransistor >> +rect 14 33 16 37 +rect 22 29 24 37 +rect 30 29 32 37 +rect 38 33 40 37 +rect 14 17 16 23 +rect 22 17 24 23 +rect 30 17 32 23 +rect 38 17 40 23 +<< ptransistor >> +rect 22 54 24 57 +rect 30 54 32 57 +<< ndiffusion >> +rect 13 33 14 37 +rect 16 33 17 37 +rect 21 33 22 37 +rect 17 29 22 33 +rect 24 29 25 37 +rect 29 29 30 37 +rect 32 33 33 37 +rect 37 33 38 37 +rect 40 33 41 37 +rect 32 29 37 33 +rect 9 21 14 23 +rect 13 17 14 21 +rect 16 17 22 23 +rect 24 17 25 23 +rect 29 17 30 23 +rect 32 17 38 23 +rect 40 21 45 23 +rect 40 17 41 21 +<< pdiffusion >> +rect 21 54 22 57 +rect 24 54 25 57 +rect 29 54 30 57 +rect 32 54 33 57 +<< ndcontact >> +rect 9 33 13 37 +rect 17 33 21 37 +rect 25 29 29 37 +rect 33 33 37 37 +rect 41 33 45 37 +rect 9 17 13 21 +rect 25 17 29 23 +rect 41 17 45 21 +<< pdcontact >> +rect 17 54 21 58 +rect 25 54 29 58 +rect 33 54 37 58 +<< psubstratepcontact >> +rect 25 9 29 13 +<< nsubstratencontact >> +rect 25 68 29 72 << polysilicon >> rect 22 57 24 60 rect 30 57 32 60 @@ -26,28 +79,13 @@ rect 14 15 16 17 rect 22 15 24 17 rect 30 15 32 17 rect 38 15 40 17 -<< ndiffusion >> -rect 13 33 14 37 -rect 16 33 17 37 -rect 21 33 22 37 -rect 17 29 22 33 -rect 24 29 25 37 -rect 29 29 30 37 -rect 32 33 33 37 -rect 37 33 38 37 -rect 40 33 41 37 -rect 32 29 37 33 -rect 9 17 14 23 -rect 16 17 22 23 -rect 24 17 25 23 -rect 29 17 30 23 -rect 32 17 38 23 -rect 40 17 45 23 -<< pdiffusion >> -rect 25 57 29 58 -rect 21 54 22 57 -rect 24 54 30 57 -rect 32 54 33 57 +<< polycontact >> +rect 27 47 31 51 +rect 10 40 14 44 +rect 23 40 27 44 +rect 40 40 44 44 +rect 12 24 16 28 +rect 38 24 42 28 << metal1 >> rect 0 68 25 72 rect 29 68 54 72 @@ -70,6 +108,17 @@ rect 29 9 54 13 rect 0 2 16 6 rect 20 2 34 6 rect 38 2 54 6 +<< m2contact >> +rect 25 68 29 72 +rect 25 54 29 58 +rect 2 33 6 37 +rect 48 33 52 37 +rect 16 24 20 28 +rect 34 24 38 28 +rect 9 17 13 21 +rect 41 17 45 21 +rect 16 2 20 6 +rect 34 2 38 6 << metal2 >> rect 2 37 6 72 rect 2 0 6 33 @@ -82,50 +131,8 @@ rect 41 21 45 72 rect 41 0 45 17 rect 48 37 52 72 rect 48 0 52 33 -<< ntransistor >> -rect 14 33 16 37 -rect 22 29 24 37 -rect 30 29 32 37 -rect 38 33 40 37 -rect 14 17 16 23 -rect 22 17 24 23 -rect 30 17 32 23 -rect 38 17 40 23 -<< ptransistor >> -rect 22 54 24 57 -rect 30 54 32 57 -<< polycontact >> -rect 27 47 31 51 -rect 10 40 14 44 -rect 23 40 27 44 -rect 40 40 44 44 -rect 12 24 16 28 -rect 38 24 42 28 -<< ndcontact >> -rect 9 33 13 37 -rect 17 33 21 37 -rect 25 29 29 37 -rect 33 33 37 37 -rect 41 33 45 37 -rect 25 17 29 23 -<< pdcontact >> -rect 17 54 21 58 -rect 33 54 37 58 -<< m2contact >> -rect 25 68 29 72 -rect 25 54 29 58 -rect 2 33 6 37 -rect 48 33 52 37 -rect 16 24 20 28 -rect 34 24 38 28 -rect 9 17 13 21 -rect 41 17 45 21 -rect 16 2 20 6 -rect 34 2 38 6 -<< psubstratepcontact >> -rect 25 9 29 13 -<< nsubstratendiff >> -rect 25 68 29 72 +<< comment >> +rect 0 0 54 70 << labels >> rlabel metal1 19 63 19 63 1 wl0 rlabel metal1 19 70 19 70 5 vdd diff --git a/technology/scn4m_subm/mag_lib/replica_cell_1w_1r.mag b/technology/scn4m_subm/mag_lib/replica_cell_1w_1r.mag index b2a525e8..61add325 100644 --- a/technology/scn4m_subm/mag_lib/replica_cell_1w_1r.mag +++ b/technology/scn4m_subm/mag_lib/replica_cell_1w_1r.mag @@ -1,10 +1,63 @@ magic tech scmos -timestamp 1572949741 -<< pwell >> -rect 0 0 54 46 +timestamp 1577067446 << nwell >> rect 0 46 54 75 +<< pwell >> +rect 0 0 54 46 +<< ntransistor >> +rect 14 33 16 37 +rect 22 29 24 37 +rect 30 29 32 37 +rect 38 33 40 37 +rect 14 17 16 23 +rect 22 17 24 23 +rect 30 17 32 23 +rect 38 17 40 23 +<< ptransistor >> +rect 22 54 24 57 +rect 30 54 32 57 +<< ndiffusion >> +rect 13 33 14 37 +rect 16 33 17 37 +rect 21 33 22 37 +rect 17 29 22 33 +rect 24 29 25 37 +rect 29 29 30 37 +rect 32 33 33 37 +rect 37 33 38 37 +rect 40 33 41 37 +rect 32 29 37 33 +rect 9 21 14 23 +rect 13 17 14 21 +rect 16 17 22 23 +rect 24 17 25 23 +rect 29 17 30 23 +rect 32 17 38 23 +rect 40 21 45 23 +rect 40 17 41 21 +<< pdiffusion >> +rect 21 54 22 57 +rect 24 54 25 57 +rect 29 54 30 57 +rect 32 54 33 57 +<< ndcontact >> +rect 9 33 13 37 +rect 17 33 21 37 +rect 25 29 29 37 +rect 33 33 37 37 +rect 41 33 45 37 +rect 9 17 13 21 +rect 25 17 29 23 +rect 41 17 45 21 +<< pdcontact >> +rect 17 54 21 58 +rect 25 54 29 58 +rect 33 54 37 58 +<< psubstratepcontact >> +rect 25 9 29 13 +<< nsubstratencontact >> +rect 25 68 29 72 << polysilicon >> rect 22 57 24 60 rect 30 57 32 60 @@ -26,28 +79,13 @@ rect 14 15 16 17 rect 22 15 24 17 rect 30 15 32 17 rect 38 15 40 17 -<< ndiffusion >> -rect 13 33 14 37 -rect 16 33 17 37 -rect 21 33 22 37 -rect 17 29 22 33 -rect 24 29 25 37 -rect 29 29 30 37 -rect 32 33 33 37 -rect 37 33 38 37 -rect 40 33 41 37 -rect 32 29 37 33 -rect 9 17 14 23 -rect 16 17 22 23 -rect 24 17 25 23 -rect 29 17 30 23 -rect 32 17 38 23 -rect 40 17 45 23 -<< pdiffusion >> -rect 25 57 29 58 -rect 21 54 22 57 -rect 24 54 30 57 -rect 32 54 33 57 +<< polycontact >> +rect 27 47 31 51 +rect 10 40 14 44 +rect 23 40 27 44 +rect 40 40 44 44 +rect 12 24 16 28 +rect 38 24 42 28 << metal1 >> rect 0 68 25 72 rect 29 68 54 72 @@ -70,6 +108,17 @@ rect 29 9 54 13 rect 0 2 16 6 rect 20 2 34 6 rect 38 2 54 6 +<< m2contact >> +rect 25 68 29 72 +rect 25 54 29 58 +rect 2 33 6 37 +rect 48 33 52 37 +rect 16 24 20 28 +rect 34 24 38 28 +rect 9 17 13 21 +rect 41 17 45 21 +rect 16 2 20 6 +rect 34 2 38 6 << metal2 >> rect 2 37 6 72 rect 2 0 6 33 @@ -82,50 +131,8 @@ rect 41 21 45 72 rect 41 0 45 17 rect 48 37 52 72 rect 48 0 52 33 -<< ntransistor >> -rect 14 33 16 37 -rect 22 29 24 37 -rect 30 29 32 37 -rect 38 33 40 37 -rect 14 17 16 23 -rect 22 17 24 23 -rect 30 17 32 23 -rect 38 17 40 23 -<< ptransistor >> -rect 22 54 24 57 -rect 30 54 32 57 -<< polycontact >> -rect 27 47 31 51 -rect 10 40 14 44 -rect 23 40 27 44 -rect 40 40 44 44 -rect 12 24 16 28 -rect 38 24 42 28 -<< ndcontact >> -rect 9 33 13 37 -rect 17 33 21 37 -rect 25 29 29 37 -rect 33 33 37 37 -rect 41 33 45 37 -rect 25 17 29 23 -<< pdcontact >> -rect 17 54 21 58 -rect 33 54 37 58 -<< m2contact >> -rect 25 68 29 72 -rect 25 54 29 58 -rect 2 33 6 37 -rect 48 33 52 37 -rect 16 24 20 28 -rect 34 24 38 28 -rect 9 17 13 21 -rect 41 17 45 21 -rect 16 2 20 6 -rect 34 2 38 6 -<< psubstratepcontact >> -rect 25 9 29 13 -<< nsubstratendiff >> -rect 25 68 29 72 +<< comment >> +rect 0 0 54 70 << labels >> rlabel metal1 19 63 19 63 1 wl0 rlabel metal1 19 70 19 70 5 vdd diff --git a/technology/scn4m_subm/mag_lib/replica_cell_6t.mag b/technology/scn4m_subm/mag_lib/replica_cell_6t.mag index 316082ca..61a7646e 100644 --- a/technology/scn4m_subm/mag_lib/replica_cell_6t.mag +++ b/technology/scn4m_subm/mag_lib/replica_cell_6t.mag @@ -1,28 +1,18 @@ magic tech scmos -timestamp 1572949776 -<< pwell >> -rect -8 -2 42 35 +timestamp 1577067503 << nwell >> rect -8 35 42 57 -<< polysilicon >> -rect 7 46 11 48 -rect 27 46 31 48 -rect 7 41 11 43 -rect 7 27 9 41 -rect 27 40 31 43 -rect 15 39 31 40 -rect 19 38 31 39 -rect 7 26 21 27 -rect 7 25 24 26 -rect 7 24 9 25 -rect 29 24 31 38 -rect 7 14 9 16 -rect 17 11 21 12 -rect 29 14 31 16 -rect -2 9 10 11 -rect 14 9 24 11 -rect 28 9 36 11 +<< pwell >> +rect -8 -2 42 35 +<< ntransistor >> +rect 7 16 9 24 +rect 29 16 31 24 +rect 10 9 14 11 +rect 24 9 28 11 +<< ptransistor >> +rect 7 43 11 46 +rect 27 43 31 46 << ndiffusion >> rect -2 22 7 24 rect 2 18 7 22 @@ -43,6 +33,45 @@ rect 2 43 7 46 rect 11 43 12 46 rect 26 43 27 46 rect 31 43 32 46 +<< ndcontact >> +rect -2 18 2 22 +rect 10 20 14 24 +rect 24 20 28 24 +rect 32 18 36 22 +rect 10 4 14 8 +rect 24 4 28 8 +<< pdcontact >> +rect -2 42 2 46 +rect 12 42 16 46 +rect 22 42 26 46 +rect 32 42 36 46 +<< psubstratepcontact >> +rect -2 28 2 32 +rect 32 28 36 32 +<< nsubstratencontact >> +rect 32 50 36 54 +<< polysilicon >> +rect 7 46 11 48 +rect 27 46 31 48 +rect 7 41 11 43 +rect 7 27 9 41 +rect 27 40 31 43 +rect 15 39 31 40 +rect 19 38 31 39 +rect 7 26 21 27 +rect 7 25 24 26 +rect 7 24 9 25 +rect 29 24 31 38 +rect 7 14 9 16 +rect 17 11 21 12 +rect 29 14 31 16 +rect -2 9 10 11 +rect 14 9 24 11 +rect 28 9 36 11 +<< polycontact >> +rect 15 35 19 39 +rect 21 26 25 30 +rect 17 12 21 16 << metal1 >> rect -2 50 15 54 rect 19 50 32 54 @@ -64,6 +93,12 @@ rect 32 22 36 28 rect -2 12 17 15 rect 21 12 36 15 rect -2 11 36 12 +<< m2contact >> +rect 15 50 19 54 +rect -2 35 2 39 +rect 32 35 36 39 +rect 6 4 10 8 +rect 20 4 24 8 << metal2 >> rect -2 39 2 54 rect -2 0 2 35 @@ -72,41 +107,8 @@ rect 6 0 10 4 rect 24 0 28 54 rect 32 39 36 54 rect 32 0 36 35 -<< ntransistor >> -rect 7 16 9 24 -rect 29 16 31 24 -rect 10 9 14 11 -rect 24 9 28 11 -<< ptransistor >> -rect 7 43 11 46 -rect 27 43 31 46 -<< polycontact >> -rect 15 35 19 39 -rect 21 26 25 30 -rect 17 12 21 16 -<< ndcontact >> -rect -2 18 2 22 -rect 10 20 14 24 -rect 24 20 28 24 -rect 32 18 36 22 -rect 10 4 14 8 -rect 24 4 28 8 -<< pdcontact >> -rect -2 42 2 46 -rect 12 42 16 46 -rect 22 42 26 46 -rect 32 42 36 46 -<< m2contact >> -rect 15 50 19 54 -rect -2 35 2 39 -rect 32 35 36 39 -rect 6 4 10 8 -rect 20 4 24 8 -<< psubstratepcontact >> -rect -2 28 2 32 -rect 32 28 36 32 -<< nsubstratencontact >> -rect 32 50 36 54 +<< bb >> +rect 0 0 34 52 << labels >> rlabel metal2 0 6 0 6 1 gnd rlabel metal2 34 6 34 6 1 gnd From 3ab99d7f9c3225672fa48af66477ef8ca985cdb4 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Tue, 24 Dec 2019 05:01:55 +0000 Subject: [PATCH 04/31] update gds library, generalize geometry reverse transform function --- compiler/base/geometry.py | 13 +++++---- compiler/bitcells/bitcell_base.py | 27 +++++++++--------- compiler/sram/sram_base.py | 8 +++--- technology/scn4m_subm/gds_lib/cell_6t.gds | Bin 5788 -> 5868 bytes technology/scn4m_subm/gds_lib/dff.gds | Bin 16622 -> 16622 bytes .../scn4m_subm/gds_lib/replica_cell_6t.gds | Bin 5868 -> 5948 bytes technology/scn4m_subm/gds_lib/sense_amp.gds | Bin 8312 -> 8312 bytes technology/scn4m_subm/gds_lib/tri_gate.gds | Bin 4576 -> 4576 bytes .../scn4m_subm/gds_lib/write_driver.gds | Bin 10204 -> 10204 bytes technology/scn4m_subm/mag_lib/cell_6t.mag | 2 +- 10 files changed, 26 insertions(+), 24 deletions(-) diff --git a/compiler/base/geometry.py b/compiler/base/geometry.py index 1c037fdf..46a7bd6e 100644 --- a/compiler/base/geometry.py +++ b/compiler/base/geometry.py @@ -256,18 +256,19 @@ class instance(geometry): new_pins.append(p) return new_pins - def reverse_bitcell_transformation(self): + def reverse_transformation(self, cell_name): path = [] - bitcell_paths = [] + cell_paths = [] pex_offsets = [] Q_offsets = [] Q_bar_offsets = [] def walk_subtree(node): path.append(node) - - if node.mod.name == 'pbitcell': - bitcell_paths.append(copy.copy(path)) + + if node.mod.name == cell_name: + print("bitcell found") + cell_paths.append(copy.copy(path)) Q_x = node.mod.get_normalized_storage_net_offset()[0][0] Q_y = node.mod.get_normalized_storage_net_offset()[0][1] @@ -338,7 +339,7 @@ class instance(geometry): return (uVector, vVector, origin) walk_subtree(self) - for path in bitcell_paths: + for path in cell_paths: vector_spaces = apply_path_transform(path) origin = vector_spaces[2] pex_offsets.append([origin[0], origin[1]]) diff --git a/compiler/bitcells/bitcell_base.py b/compiler/bitcells/bitcell_base.py index ea394548..3661abf7 100644 --- a/compiler/bitcells/bitcell_base.py +++ b/compiler/bitcells/bitcell_base.py @@ -10,7 +10,7 @@ import debug import design from globals import OPTS import logical_effort -from tech import parameter, drc +from tech import parameter, drc, layer class bitcell_base(design.design): @@ -85,14 +85,15 @@ class bitcell_base(design.design): Gets the location of the storage net labels to add top level labels for pex simulation. """ - #TODO: use getTexts to support custom bitcells # If we generated the bitcell, we already know where Q and Q_bar are - #if OPTS.bitcell is not "pbitcell": - # self.storage_net_offsets = [] - # for net in get_storage_net_names: - # if net is "Q" or "Q_bar": - # for text in self.getTexts("metal1"): - # self.storage_net_offsets.append(text.offsetInMicrons) + if OPTS.bitcell is not "pbitcell": + self.storage_net_offsets = [] + for i in range(0, len(self.get_storage_net_names())): + for text in self.gds.getTexts(layer["metal1"]): + if self.storage_nets[i] == text: + print(text) + + return(self.storage_net_offsets) def get_normalized_storage_net_offset(self): @@ -101,11 +102,11 @@ class bitcell_base(design.design): of the bitcell. This is useful for making sense of offsets outside of the bitcell. """ - - Q_x = self.storage_net_offsets[0][0] - self.leftmost_xpos - Q_y = self.storage_net_offsets[0][1] - self.botmost_ypos - Q_bar_x = self.storage_net_offsets[1][0] - self.leftmost_xpos - Q_bar_y = self.storage_net_offsets[1][1] - self.botmost_ypos + print("get normalized") + Q_x = self.get_storage_net_offset()[0][0] - self.leftmost_xpos + Q_y = self.get_storage_net_offset()[0][1] - self.botmost_ypos + Q_bar_x = self.get_storage_net_offset()[1][0] - self.leftmost_xpos + Q_bar_y = self.get_storage_net_offset()[1][1] - self.botmost_ypos normalized_storage_net_offset = [[Q_x,Q_y],[Q_bar_x,Q_bar_y]] diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index cd9fb19d..6a7e996e 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -94,21 +94,21 @@ class sram_base(design, verilog, lef): # add pex labels for bitcell for bank_num in range(0,len(self.bank_insts)): bank = self.bank_insts[bank_num] - pex_offsets = bank.reverse_bitcell_transformation() + pex_offsets = bank.reverse_transformation(bank.mod.bitcell.name) bank_offset = pex_offsets[0] # offset bank relative to sram Q_offset = pex_offsets[1] # offset of storage relative to bank Q_bar_offset = pex_offsets[2] # offset of storage relative to bank - layer = "metal1" + layer_name = "metal1" for i in range(0,len(bank_offset)): Q = [bank_offset[i][0] + Q_offset[i][0], bank_offset[i][1] + Q_offset[i][1]] Q_bar = [bank_offset[i][0] + Q_bar_offset[i][0], bank_offset[i][1] + Q_bar_offset[i][1]] - self.add_layout_pin_rect_center("bitcell_Q_b{0}_r{1}_c{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , layer, Q) - self.add_layout_pin_rect_center("bitcell_Q_bar_b{0}_r{1}_c{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)), layer, Q_bar) + self.add_layout_pin_rect_center("bitcell_Q_b{0}_r{1}_c{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , layer_name, Q) + self.add_layout_pin_rect_center("bitcell_Q_bar_b{0}_r{1}_c{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)), layer_name, Q_bar) # add pex labels for control logic for i in range (0,len(self.control_logic_insts)): diff --git a/technology/scn4m_subm/gds_lib/cell_6t.gds b/technology/scn4m_subm/gds_lib/cell_6t.gds index 14d6ab7e9697c2a197b595db62ac8c2e7db6d325..6bfc44317b701b019ff7e4dadbefdf591068e370 100644 GIT binary patch delta 118 zcmbQE`$kuZfsKKQftf*uk%^(4frmkYfrY`GK?u&aVBnjmq%Mk8Vq=_z*yI8+5guL- s1_qfI3~Z8Yfee$g#H3^de=snJK49Pi3dAQR7BMie2m&!X5VJ4<0F8_gBLDyZ delta 75 zcmaE(J4aWEfsKKQftf*uk%^%k$QESaXW(EEgR?mqq$Vn7D delta 88 zcmaE${6JZWfsKKQftf*uk%^&n*vXG#}WER0Y02G@KKmY&$ diff --git a/technology/scn4m_subm/gds_lib/write_driver.gds b/technology/scn4m_subm/gds_lib/write_driver.gds index 8223c795bae070e4d734e567c739a4440f0194ac..9e201f2402bc21fcd17da3b25c62a80d3ffc20b1 100644 GIT binary patch delta 64 zcmccPf5%^mfsKKQftf*uk%^(4fddG|7&I9~fovWIaiEL@1M@^BeL)PtjY(DN01eIu A=Kufz delta 64 vcmccPf5%^mfsKKQftf*uk%^(4fddHn88jJ0;cP7izKKfuf*67uld9AK4w?uD diff --git a/technology/scn4m_subm/mag_lib/cell_6t.mag b/technology/scn4m_subm/mag_lib/cell_6t.mag index 17206ac6..e8c16eff 100644 --- a/technology/scn4m_subm/mag_lib/cell_6t.mag +++ b/technology/scn4m_subm/mag_lib/cell_6t.mag @@ -1,6 +1,6 @@ magic tech scmos -timestamp 1577066121 +timestamp 1577163318 << nwell >> rect -8 35 42 57 << pwell >> From 05ab018ffc31ce90a7fa04e801a4b2d2c0c63387 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Tue, 7 Jan 2020 00:01:32 +0000 Subject: [PATCH 05/31] strip padding character from gds reading --- compiler/bitcells/bitcell_base.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler/bitcells/bitcell_base.py b/compiler/bitcells/bitcell_base.py index 3661abf7..62bcf1bb 100644 --- a/compiler/bitcells/bitcell_base.py +++ b/compiler/bitcells/bitcell_base.py @@ -90,8 +90,8 @@ class bitcell_base(design.design): self.storage_net_offsets = [] for i in range(0, len(self.get_storage_net_names())): for text in self.gds.getTexts(layer["metal1"]): - if self.storage_nets[i] == text: - print(text) + if self.storage_nets[i] == text.textString.rstrip('\x00'): + print(text.textString + "sucess") return(self.storage_net_offsets) From 2733c3bf3fe2acd23b6d89f9a8e7ca2c27b8e326 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Wed, 15 Jan 2020 09:00:02 +0000 Subject: [PATCH 06/31] fix custom bitcell labeling; fix gds scaling in labeling --- compiler/base/geometry.py | 11 ++++---- compiler/bitcells/bitcell.py | 4 +-- compiler/bitcells/bitcell_base.py | 25 ++++++++++++------- technology/scn4m_subm/sp_lib/cell_6t.sp | 10 ++++---- technology/scn4m_subm/sp_lib/dummy_cell_6t.sp | 10 ++++---- 5 files changed, 34 insertions(+), 26 deletions(-) diff --git a/compiler/base/geometry.py b/compiler/base/geometry.py index 46a7bd6e..885b139a 100644 --- a/compiler/base/geometry.py +++ b/compiler/base/geometry.py @@ -267,14 +267,15 @@ class instance(geometry): path.append(node) if node.mod.name == cell_name: - print("bitcell found") cell_paths.append(copy.copy(path)) + + normalized_storage_nets = node.mod.get_normalized_storage_nets_offset() - Q_x = node.mod.get_normalized_storage_net_offset()[0][0] - Q_y = node.mod.get_normalized_storage_net_offset()[0][1] + Q_x = normalized_storage_nets[0][0] + Q_y = normalized_storage_nets[0][1] - Q_bar_x = node.mod.get_normalized_storage_net_offset()[1][0] - Q_bar_y = node.mod.get_normalized_storage_net_offset()[1][1] + Q_bar_x = normalized_storage_nets[1][0] + Q_bar_y = normalized_storage_nets[1][1] if node.mirror == 'MX': Q_y = -1 * Q_y diff --git a/compiler/bitcells/bitcell.py b/compiler/bitcells/bitcell.py index b22c9a46..52552413 100644 --- a/compiler/bitcells/bitcell.py +++ b/compiler/bitcells/bitcell.py @@ -18,9 +18,9 @@ class bitcell(bitcell_base.bitcell_base): the layout and netlist should be available in the technology library. """ - + pin_names = ["bl", "br", "wl", "vdd", "gnd"] - storage_nets = ['Q', 'Qbar'] + storage_nets = ['Q', 'Q_bar'] type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"] (width, height) = utils.get_libcell_size("cell_6t", GDS["unit"], diff --git a/compiler/bitcells/bitcell_base.py b/compiler/bitcells/bitcell_base.py index 62bcf1bb..0a5624bd 100644 --- a/compiler/bitcells/bitcell_base.py +++ b/compiler/bitcells/bitcell_base.py @@ -88,27 +88,34 @@ class bitcell_base(design.design): # If we generated the bitcell, we already know where Q and Q_bar are if OPTS.bitcell is not "pbitcell": self.storage_net_offsets = [] - for i in range(0, len(self.get_storage_net_names())): + for i in range(len(self.get_storage_net_names())): for text in self.gds.getTexts(layer["metal1"]): if self.storage_nets[i] == text.textString.rstrip('\x00'): - print(text.textString + "sucess") + self.storage_net_offsets.append(text.coordinates[0]) + for i in range(len(self.storage_net_offsets)): + self.storage_net_offsets[i] = tuple([self.gds.info["units"][0] * x for x in self.storage_net_offsets[i]]) + return(self.storage_net_offsets) - def get_normalized_storage_net_offset(self): + def get_normalized_storage_nets_offset(self): """ Convert storage net offset to be relative to the bottom left corner of the bitcell. This is useful for making sense of offsets outside of the bitcell. """ - print("get normalized") - Q_x = self.get_storage_net_offset()[0][0] - self.leftmost_xpos - Q_y = self.get_storage_net_offset()[0][1] - self.botmost_ypos - Q_bar_x = self.get_storage_net_offset()[1][0] - self.leftmost_xpos - Q_bar_y = self.get_storage_net_offset()[1][1] - self.botmost_ypos + if OPTS.bitcell is not "pbitcell": + normalized_storage_net_offset = self.get_storage_net_offset() - normalized_storage_net_offset = [[Q_x,Q_y],[Q_bar_x,Q_bar_y]] + else: + net_offset = self.get_storage_net_offset() + Q_x = net_offset[0][0] - self.leftmost_xpos + Q_y = net_offset[0][1] - self.botmost_ypos + Q_bar_x = net_offset[1][0] - self.leftmost_xpos + Q_bar_y = net_offset[1][1] - self.botmost_ypos + + normalized_storage_net_offset = [[Q_x,Q_y],[Q_bar_x,Q_bar_y]] return normalized_storage_net_offset diff --git a/technology/scn4m_subm/sp_lib/cell_6t.sp b/technology/scn4m_subm/sp_lib/cell_6t.sp index bb430893..dc724007 100644 --- a/technology/scn4m_subm/sp_lib/cell_6t.sp +++ b/technology/scn4m_subm/sp_lib/cell_6t.sp @@ -4,15 +4,15 @@ * SPICE3 file created from cell_6t.ext - technology: scmos * Inverter 1 -M1000 Q Qbar vdd vdd p w=0.6u l=0.8u -M1002 Q Qbar gnd gnd n w=1.6u l=0.4u +M1000 Q Q_bar vdd vdd p w=0.6u l=0.8u +M1002 Q Q_bar gnd gnd n w=1.6u l=0.4u * Inverter 2 -M1001 vdd Q Qbar vdd p w=0.6u l=0.8u -M1003 gnd Q Qbar gnd n w=1.6u l=0.4u +M1001 vdd Q Q_bar vdd p w=0.6u l=0.8u +M1003 gnd Q Q_bar gnd n w=1.6u l=0.4u * Access transistors M1004 Q wl bl gnd n w=0.8u l=0.4u -M1005 Qbar wl br gnd n w=0.8u l=0.4u +M1005 Q_bar wl br gnd n w=0.8u l=0.4u .ENDS diff --git a/technology/scn4m_subm/sp_lib/dummy_cell_6t.sp b/technology/scn4m_subm/sp_lib/dummy_cell_6t.sp index 3b0584df..c5b6ff9d 100644 --- a/technology/scn4m_subm/sp_lib/dummy_cell_6t.sp +++ b/technology/scn4m_subm/sp_lib/dummy_cell_6t.sp @@ -3,15 +3,15 @@ .SUBCKT dummy_cell_6t bl br wl vdd gnd * Inverter 1 -M1000 Q Qbar vdd vdd p w=0.6u l=0.8u -M1002 Q Qbar gnd gnd n w=1.6u l=0.4u +M1000 Q Q_bar vdd vdd p w=0.6u l=0.8u +M1002 Q Q_bar gnd gnd n w=1.6u l=0.4u * Inverter 2 -M1001 vdd Q Qbar vdd p w=0.6u l=0.8u -M1003 gnd Q Qbar gnd n w=1.6u l=0.4u +M1001 vdd Q Q_bar vdd p w=0.6u l=0.8u +M1003 gnd Q Q_bar gnd n w=1.6u l=0.4u * Access transistors M1004 Q wl bl_noconn gnd n w=0.8u l=0.4u -M1005 Qbar wl br_noconn gnd n w=0.8u l=0.4u +M1005 Q_bar wl br_noconn gnd n w=0.8u l=0.4u .ENDS From 075bf0d841c2c8413fe114d732941baba5e1785c Mon Sep 17 00:00:00 2001 From: jcirimel Date: Thu, 16 Jan 2020 03:51:29 -0800 Subject: [PATCH 07/31] label bitcell in stim, add s_en top level to stim --- compiler/characterizer/delay.py | 7 +++++-- compiler/characterizer/stimuli.py | 10 ++++++---- compiler/sram/sram_1bank.py | 3 +++ compiler/verify/magic.py | 20 +++++++++++++------- 4 files changed, 27 insertions(+), 13 deletions(-) diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index e64f9515..60039f89 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -221,8 +221,9 @@ class delay(simulation): q_name = cell_name+'.'+str(storage_names[0]) qbar_name = cell_name+'.'+str(storage_names[1]) else: - q_name = "bitcell_Q_r{0}_c{1}".format(OPTS.num_words -1, OPTS.word_size-1) - qbar_name = "bitcell_Q_r{0}_c{1}".format(OPTS.num_words -1, OPTS.word_size-1) + bank_num = self.sram.get_bank_num(self.sram.name, bit_row, bit_col) + q_name = "bitcell_Q_b{0}_r{1}_c{2}".format(bank_num, bit_row, bit_col) + qbar_name = "bitcell_Q_bar_b{0}_r{1}_c{2}".format(bank_num, bit_row, bit_col) # Bit measures, measurements times to be defined later. The measurement names must be unique # but they is enforced externally @@ -284,6 +285,8 @@ class delay(simulation): debug.check(len(sa_mods) == 1, "Only expected one type of Sense Amp. Cannot perform s_en checks.") enable_name = sa_mods[0].get_enable_name() sen_name = self.get_alias_in_path(paths, enable_name, sa_mods[0]) + if OPTS.use_pex: + #get sense amp multi bank return sen_name def get_bl_name(self, paths, port): diff --git a/compiler/characterizer/stimuli.py b/compiler/characterizer/stimuli.py index e565fb5f..5d08fbf9 100644 --- a/compiler/characterizer/stimuli.py +++ b/compiler/characterizer/stimuli.py @@ -52,10 +52,12 @@ class stimuli(): for pin in pins: self.sf.write("{0} ".format(pin)) if OPTS.use_pex: - for row in range(0,OPTS.num_words): - for col in range(0,OPTS.word_size): - self.sf.write("bitcell_Q_r{0}_c{1} ".format(row,col)) - self.sf.write("bitcell_Q_bar_r{0}_c{1} ".format(row,col)) + for bank in range(OPTS.num_banks): + for row in range(OPTS.num_words): + for col in range(OPTS.word_size): + self.sf.write("bitcell_Q_b{0}_r{1}_c{2} ".format(bank,row,col)) + self.sf.write("bitcell_Q_bar_b{0}_r{1}_c{2} ".format(bank,row,col)) + self.sf.write("s_en{0} ".format(bank)) self.sf.write("{0}\n".format(model_name)) diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py index 9e578c7c..c07b43e5 100644 --- a/compiler/sram/sram_1bank.py +++ b/compiler/sram/sram_1bank.py @@ -489,3 +489,6 @@ class sram_1bank(sram_base): if inst_name.find('x') != 0: inst_name = 'x'+inst_name return self.bank_inst.mod.get_cell_name(inst_name+'.x'+self.bank_inst.name, row, col) + + def get_bank_num(self, inst_name, row, col): + return 0; diff --git a/compiler/verify/magic.py b/compiler/verify/magic.py index fb0bc452..fa219e77 100644 --- a/compiler/verify/magic.py +++ b/compiler/verify/magic.py @@ -309,7 +309,7 @@ def run_pex(name, gds_name, sp_name, output=None, final_verification=False): out_errors = find_error(results) debug.check(os.path.isfile(output),"Couldn't find PEX extracted output.") - #correct_port(name,output,sp_name) + correct_port(name,output,sp_name) return out_errors def write_batch_pex_rule(gds_name,name,sp_name,output): @@ -375,7 +375,7 @@ def write_script_pex_rule(gds_name,cell_name,output): else: pre = "" f.write(pre+"extract\n".format(cell_name)) - f.write(pre+"ext2spice hierarchy on\n") + f.write(pre+"ext2spice hierarchy off\n") f.write(pre+"ext2spice format ngspice\n") f.write(pre+"ext2spice renumber off\n") f.write(pre+"ext2spice scale off\n") @@ -414,14 +414,20 @@ def correct_port(name, output_file_name, ref_file_name): part2 = pex_file.read() bitcell_list = "+ " - for row in range(0,OPTS.num_words): - for col in range(0,OPTS.word_size): - bitcell_list += "bitcell_Q_r{0}_c{1} ".format(row,col) - bitcell_list += "bitcell_Q_bar_r{0}_c{1} ".format(row,col) + for bank in range(OPTS.num_banks): + for row in range(OPTS.num_words): + for col in range(OPTS.word_size): + bitcell_list += "bitcell_Q_b{0}_r{1}_c{2} ".format(bank, row,col) + bitcell_list += "bitcell_Q_bar_b{0}_r{1}_c{2} ".format(bank, row,col) bitcell_list += "\n" + control_list = "+ " + for bank in range(OPTS.num_banks): + control_list += "s_en{0}".format(bank) + control_list += '\n' + + part2 = bitcell_list + control_list + part2 - part2 = bitcell_list + part2 pex_file.close() # obtain the correct definition line from the original spice file From 364842569a0dec098bdb51bd64dedfa630d6317e Mon Sep 17 00:00:00 2001 From: jcirimel Date: Thu, 16 Jan 2020 12:16:49 -0800 Subject: [PATCH 08/31] fix s_en in stim --- compiler/characterizer/delay.py | 2 +- compiler/sram/sram_1bank.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index 60039f89..f53e91a6 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -286,7 +286,7 @@ class delay(simulation): enable_name = sa_mods[0].get_enable_name() sen_name = self.get_alias_in_path(paths, enable_name, sa_mods[0]) if OPTS.use_pex: - #get sense amp multi bank + sen_name = sen_name.split('.')[-1] return sen_name def get_bl_name(self, paths, port): diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py index c07b43e5..a141765b 100644 --- a/compiler/sram/sram_1bank.py +++ b/compiler/sram/sram_1bank.py @@ -480,7 +480,7 @@ class sram_1bank(sram_base): debug.error("Signal={} not contained in control logic connections={}"\ .format(sen_name, control_conns)) if sen_name in self.pins: - debug.error("Internal signal={} contained in port list. Name defined by the parent.") + debug.error("Internal signal={} contained in port list. Name defined by the parent.") return "X{}.{}".format(sram_name, sen_name) def get_cell_name(self, inst_name, row, col): From 5778901cfe84219f722879ae09aa79f6476b1024 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Mon, 20 Jan 2020 12:16:30 +0000 Subject: [PATCH 09/31] pull bitline labels to top level spice --- compiler/base/geometry.py | 122 ++++++++++++++++-------------- compiler/bitcells/bitcell_base.py | 15 ++++ compiler/sram/sram_base.py | 27 +++++-- 3 files changed, 101 insertions(+), 63 deletions(-) diff --git a/compiler/base/geometry.py b/compiler/base/geometry.py index 885b139a..0fef7b72 100644 --- a/compiler/base/geometry.py +++ b/compiler/base/geometry.py @@ -255,13 +255,64 @@ class instance(geometry): p.transform(self.offset,self.mirror,self.rotate) new_pins.append(p) return new_pins + + def calculate_transform(self, node): + #set up the rotation matrix + angle = math.radians(float(node.rotate)) + mRotate = np.array([[math.cos(angle),-math.sin(angle),0.0], + [math.sin(angle),math.cos(angle),0.0], + [0.0,0.0,1.0]]) - def reverse_transformation(self, cell_name): + #set up translation matrix + translateX = float(node.offset[0]) + translateY = float(node.offset[1]) + mTranslate = np.array([[1.0,0.0,translateX], + [0.0,1.0,translateY], + [0.0,0.0,1.0]]) + + #set up the scale matrix (handles mirror X) + scaleX = 1.0 + if(node.mirror == 'MX'): + scaleY = -1.0 + else: + scaleY = 1.0 + mScale = np.array([[scaleX,0.0,0.0], + [0.0,scaleY,0.0], + [0.0,0.0,1.0]]) + + return (mRotate, mScale, mTranslate) + + def apply_transform(self, mtransforms, uVector, vVector, origin): + origin = np.dot(mtransforms[0], origin) #rotate + uVector = np.dot(mtransforms[0], uVector) #rotate + vVector = np.dot(mtransforms[0], vVector) #rotate + origin = np.dot(mtransforms[1], origin) #scale + uVector = np.dot(mtransforms[1], uVector) #scale + vVector = np.dot(mtransforms[1], vVector) #scale + origin = np.dot(mtransforms[2], origin) + + return(uVector, vVector, origin) + + def apply_path_transform(self, path): + uVector = np.array([[1.0],[0.0],[0.0]]) + vVector = np.array([[0.0],[1.0],[0.0]]) + origin = np.array([[0.0],[0.0],[1.0]]) + + while(path): + instance = path.pop(-1) + mtransforms = self.calculate_transform(instance) + (uVector, vVector, origin) = self.apply_transform(mtransforms, uVector, vVector, origin) + + return (uVector, vVector, origin) + + def reverse_transformation_bitcell(self, cell_name): path = [] cell_paths = [] - pex_offsets = [] + origin_offsets = [] Q_offsets = [] Q_bar_offsets = [] + bl_offsets = [] + br_offsets = [] def walk_subtree(node): path.append(node) @@ -270,6 +321,7 @@ class instance(geometry): cell_paths.append(copy.copy(path)) normalized_storage_nets = node.mod.get_normalized_storage_nets_offset() + normalized_bitline_nets = node.mod.get_normalized_bitline_offset() Q_x = normalized_storage_nets[0][0] Q_y = normalized_storage_nets[0][1] @@ -277,75 +329,35 @@ class instance(geometry): Q_bar_x = normalized_storage_nets[1][0] Q_bar_y = normalized_storage_nets[1][1] + bl_x = normalized_bitline_nets[0][0] + bl_y = normalized_bitline_nets[0][1] + + br_x = normalized_bitline_nets[1][0] + br_y = normalized_bitline_nets[1][1] + if node.mirror == 'MX': Q_y = -1 * Q_y Q_bar_y = -1 * Q_bar_y + bl_y = -1 * bl_y + br_y = -1 * br_y Q_offsets.append([Q_x, Q_y]) Q_bar_offsets.append([Q_bar_x, Q_bar_y]) - + bl_offsets.append([bl_x, bl_y]) + br_offsets.append([br_x, br_y]) elif node.mod.insts is not []: for instance in node.mod.insts: walk_subtree(instance) path.pop(-1) - def calculate_transform(node): - #set up the rotation matrix - angle = math.radians(float(node.rotate)) - mRotate = np.array([[math.cos(angle),-math.sin(angle),0.0], - [math.sin(angle),math.cos(angle),0.0], - [0.0,0.0,1.0]]) - - #set up translation matrix - translateX = float(node.offset[0]) - translateY = float(node.offset[1]) - mTranslate = np.array([[1.0,0.0,translateX], - [0.0,1.0,translateY], - [0.0,0.0,1.0]]) - - #set up the scale matrix (handles mirror X) - scaleX = 1.0 - if(node.mirror == 'MX'): - scaleY = -1.0 - else: - scaleY = 1.0 - mScale = np.array([[scaleX,0.0,0.0], - [0.0,scaleY,0.0], - [0.0,0.0,1.0]]) - - return (mRotate, mScale, mTranslate) - - def apply_transform(mtransforms, uVector, vVector, origin): - origin = np.dot(mtransforms[0], origin) #rotate - uVector = np.dot(mtransforms[0], uVector) #rotate - vVector = np.dot(mtransforms[0], vVector) #rotate - origin = np.dot(mtransforms[1], origin) #scale - uVector = np.dot(mtransforms[1], uVector) #scale - vVector = np.dot(mtransforms[1], vVector) #scale - origin = np.dot(mtransforms[2], origin) - - return(uVector, vVector, origin) - - def apply_path_transform(path): - uVector = np.array([[1.0],[0.0],[0.0]]) - vVector = np.array([[0.0],[1.0],[0.0]]) - origin = np.array([[0.0],[0.0],[1.0]]) - - while(path): - instance = path.pop(-1) - mtransforms = calculate_transform(instance) - (uVector, vVector, origin) = apply_transform(mtransforms, uVector, vVector, origin) - - return (uVector, vVector, origin) - walk_subtree(self) for path in cell_paths: - vector_spaces = apply_path_transform(path) + vector_spaces = self.apply_path_transform(path) origin = vector_spaces[2] - pex_offsets.append([origin[0], origin[1]]) + origin_offsets.append([origin[0], origin[1]]) - return(pex_offsets, Q_offsets, Q_bar_offsets) + return(origin_offsets, Q_offsets, Q_bar_offsets, bl_offsets, br_offsets) def __str__(self): """ override print function output """ diff --git a/compiler/bitcells/bitcell_base.py b/compiler/bitcells/bitcell_base.py index 0a5624bd..56c36b66 100644 --- a/compiler/bitcells/bitcell_base.py +++ b/compiler/bitcells/bitcell_base.py @@ -99,6 +99,19 @@ class bitcell_base(design.design): return(self.storage_net_offsets) + def get_bitline_offset(self): + self.bitline_names = ["bl", "br"] + self.bitline_offsets = [] + for i in range(len(self.bitline_names)): + for text in self.gds.getTexts(layer["metal2"]): + if self.bitline_names[i] == text.textString.rstrip('\x00'): + self.bitline_offsets.append(text.coordinates[0]) + + for i in range(len(self.bitline_offsets)): + self.bitline_offsets[i] = tuple([self.gds.info["units"][0] * x for x in self.bitline_offsets[i]]) + + return(self.bitline_offsets) + def get_normalized_storage_nets_offset(self): """ Convert storage net offset to be relative to the bottom left corner @@ -119,6 +132,8 @@ class bitcell_base(design.design): return normalized_storage_net_offset + def get_normalized_bitline_offset(self): + return self.get_bitline_offset() def build_graph(self, graph, inst_name, port_nets): """ diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index 6a7e996e..1a8d220b 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -91,34 +91,45 @@ class sram_base(design, verilog, lef): Add pex labels at the sram level for spice analysis """ - # add pex labels for bitcell - for bank_num in range(0,len(self.bank_insts)): + # add pex labels for bitcells + for bank_num in range(len(self.bank_insts)): bank = self.bank_insts[bank_num] - pex_offsets = bank.reverse_transformation(bank.mod.bitcell.name) + pex_offsets = bank.reverse_transformation_bitcell(bank.mod.bitcell.name) bank_offset = pex_offsets[0] # offset bank relative to sram Q_offset = pex_offsets[1] # offset of storage relative to bank Q_bar_offset = pex_offsets[2] # offset of storage relative to bank + bl_offsets = pex_offsets[3] + br_offsets = pex_offsets[4] - layer_name = "metal1" + storage_layer_name = "metal1" + bitline_layer_name = "metal2" for i in range(0,len(bank_offset)): Q = [bank_offset[i][0] + Q_offset[i][0], bank_offset[i][1] + Q_offset[i][1]] Q_bar = [bank_offset[i][0] + Q_bar_offset[i][0], bank_offset[i][1] + Q_bar_offset[i][1]] + bl = [bank_offset[i][0] + bl_offsets[i][0], bank_offset[i][1] + bl_offsets[i][1]] + br = [bank_offset[i][0] + br_offsets[i][0], bank_offset[i][1] + br_offsets[i][1]] - self.add_layout_pin_rect_center("bitcell_Q_b{0}_r{1}_c{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , layer_name, Q) - self.add_layout_pin_rect_center("bitcell_Q_bar_b{0}_r{1}_c{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)), layer_name, Q_bar) + self.add_layout_pin_rect_center("bitcell_Q_b{0}_r{1}_c{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , storage_layer_name, Q) + self.add_layout_pin_rect_center("bitcell_Q_bar_b{0}_r{1}_c{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)), storage_layer_name, Q_bar) + + self.add_layout_pin_rect_center("bitcell_bl_b{0}_c{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , bitline_layer_name, bl) + self.add_layout_pin_rect_center("bitcell_br_b{0}_c{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)), bitline_layer_name, br) + + + # add pex labels for control logic - for i in range (0,len(self.control_logic_insts)): + for i in range (len(self.control_logic_insts)): instance = self.control_logic_insts[i] control_logic_offset = instance.offset for output in instance.mod.output_list: pin = instance.mod.get_pin(output) pin.transform([0,0], instance.mirror, instance.rotate) offset = [control_logic_offset[0] + pin.center()[0], control_logic_offset[1] + pin.center()[1]] - self.add_layout_pin_rect_center("{0}{1}".format(pin.name,i), "metal1", offset) + self.add_layout_pin_rect_center("{0}{1}".format(pin.name,i), storage_layer_name, offset) From 73691f60548d87791d70c3224f664c1c6d5a792c Mon Sep 17 00:00:00 2001 From: jcirimel Date: Tue, 21 Jan 2020 00:20:52 -0800 Subject: [PATCH 10/31] fix bug in top level bitline label placement --- compiler/bitcells/bitcell_base.py | 8 ++++++-- compiler/characterizer/delay.py | 5 ++++- compiler/characterizer/stimuli.py | 3 +++ compiler/sram/sram_base.py | 4 ++-- compiler/verify/magic.py | 3 +++ 5 files changed, 18 insertions(+), 5 deletions(-) diff --git a/compiler/bitcells/bitcell_base.py b/compiler/bitcells/bitcell_base.py index 56c36b66..f0f562c6 100644 --- a/compiler/bitcells/bitcell_base.py +++ b/compiler/bitcells/bitcell_base.py @@ -101,11 +101,15 @@ class bitcell_base(design.design): def get_bitline_offset(self): self.bitline_names = ["bl", "br"] + found_bitlines = [] self.bitline_offsets = [] for i in range(len(self.bitline_names)): for text in self.gds.getTexts(layer["metal2"]): - if self.bitline_names[i] == text.textString.rstrip('\x00'): - self.bitline_offsets.append(text.coordinates[0]) + if not self.bitline_names[i] in found_bitlines: + if self.bitline_names[i] == text.textString.rstrip('\x00'): + self.bitline_offsets.append(text.coordinates[0]) + found_bitlines.append(self.bitline_names[i]) + continue for i in range(len(self.bitline_offsets)): self.bitline_offsets[i] = tuple([self.gds.info["units"][0] * x for x in self.bitline_offsets[i]]) diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index f53e91a6..3aa2765a 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -302,7 +302,10 @@ class delay(simulation): exclude_set = self.get_bl_name_search_exclusions() for int_net in [cell_bl, cell_br]: bl_names.append(self.get_alias_in_path(paths, int_net, cell_mod, exclude_set)) - + #if OPTS.use_pex: + # bank_num = 0 + # bl_names[0] = "bl_b{0}_{1}".format(bank_num, ) + # bl_names[1] = "br_b{0}_{1}".format(bank_num, ) return bl_names[0], bl_names[1] diff --git a/compiler/characterizer/stimuli.py b/compiler/characterizer/stimuli.py index 5d08fbf9..28a02472 100644 --- a/compiler/characterizer/stimuli.py +++ b/compiler/characterizer/stimuli.py @@ -57,6 +57,9 @@ class stimuli(): for col in range(OPTS.word_size): self.sf.write("bitcell_Q_b{0}_r{1}_c{2} ".format(bank,row,col)) self.sf.write("bitcell_Q_bar_b{0}_r{1}_c{2} ".format(bank,row,col)) + for col in range(OPTS.word_size): + self.sf.write("bl_b{0}_c{2} ".format(bank, row,col)) + self.sf.write("br_b{0}_c{2} ".format(bank, row,col)) self.sf.write("s_en{0} ".format(bank)) self.sf.write("{0}\n".format(model_name)) diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index 1a8d220b..5fc510b7 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -115,8 +115,8 @@ class sram_base(design, verilog, lef): self.add_layout_pin_rect_center("bitcell_Q_b{0}_r{1}_c{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , storage_layer_name, Q) self.add_layout_pin_rect_center("bitcell_Q_bar_b{0}_r{1}_c{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)), storage_layer_name, Q_bar) - self.add_layout_pin_rect_center("bitcell_bl_b{0}_c{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , bitline_layer_name, bl) - self.add_layout_pin_rect_center("bitcell_br_b{0}_c{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)), bitline_layer_name, br) + self.add_layout_pin_rect_center("bl_b{0}_{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , bitline_layer_name, bl) + self.add_layout_pin_rect_center("br_b{0}_{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)), bitline_layer_name, br) diff --git a/compiler/verify/magic.py b/compiler/verify/magic.py index fa219e77..29014797 100644 --- a/compiler/verify/magic.py +++ b/compiler/verify/magic.py @@ -419,6 +419,9 @@ def correct_port(name, output_file_name, ref_file_name): for col in range(OPTS.word_size): bitcell_list += "bitcell_Q_b{0}_r{1}_c{2} ".format(bank, row,col) bitcell_list += "bitcell_Q_bar_b{0}_r{1}_c{2} ".format(bank, row,col) + for col in range(OPTS.word_size): + bitcell_list += "bl_b{0}_c{2} ".format(bank, row,col) + bitcell_list += "br_b{0}_c{2} ".format(bank, row,col) bitcell_list += "\n" control_list = "+ " From 40c01dab855bb651c0504f02503f02649743096a Mon Sep 17 00:00:00 2001 From: jcirimel Date: Tue, 21 Jan 2020 01:44:15 -0800 Subject: [PATCH 11/31] fix bl in stim file --- compiler/characterizer/delay.py | 16 ++++++++++------ compiler/characterizer/stimuli.py | 29 +++++++++++++++++++---------- compiler/sram/sram_base.py | 8 ++++++-- compiler/verify/magic.py | 8 ++++++-- 4 files changed, 41 insertions(+), 20 deletions(-) diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index 3aa2765a..6ec3ae8a 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -302,10 +302,9 @@ class delay(simulation): exclude_set = self.get_bl_name_search_exclusions() for int_net in [cell_bl, cell_br]: bl_names.append(self.get_alias_in_path(paths, int_net, cell_mod, exclude_set)) - #if OPTS.use_pex: - # bank_num = 0 - # bl_names[0] = "bl_b{0}_{1}".format(bank_num, ) - # bl_names[1] = "br_b{0}_{1}".format(bank_num, ) + if OPTS.use_pex: + for i in range(len(bl_names)): + bl_names[i] = bl_names[i].split('.')[-1] return bl_names[0], bl_names[1] @@ -396,8 +395,13 @@ class delay(simulation): # instantiate the sram self.sf.write("\n* Instantiation of the SRAM\n") - self.stim.inst_model(pins=self.pins, - model_name=self.sram.name) + if not OPTS.use_pex: + self.stim.inst_model(pins=self.pins, + model_name=self.sram.name) + else: + self.stim.inst_sram_pex(pins=self.pins, + model_name=self.sram.name) + self.sf.write("\n* SRAM output loads\n") for port in self.read_ports: for i in range(self.word_size): diff --git a/compiler/characterizer/stimuli.py b/compiler/characterizer/stimuli.py index 28a02472..f413d97b 100644 --- a/compiler/characterizer/stimuli.py +++ b/compiler/characterizer/stimuli.py @@ -51,18 +51,27 @@ class stimuli(): self.sf.write("X{0} ".format(model_name)) for pin in pins: self.sf.write("{0} ".format(pin)) - if OPTS.use_pex: - for bank in range(OPTS.num_banks): - for row in range(OPTS.num_words): - for col in range(OPTS.word_size): - self.sf.write("bitcell_Q_b{0}_r{1}_c{2} ".format(bank,row,col)) - self.sf.write("bitcell_Q_bar_b{0}_r{1}_c{2} ".format(bank,row,col)) - for col in range(OPTS.word_size): - self.sf.write("bl_b{0}_c{2} ".format(bank, row,col)) - self.sf.write("br_b{0}_c{2} ".format(bank, row,col)) - self.sf.write("s_en{0} ".format(bank)) self.sf.write("{0}\n".format(model_name)) + + def inst_sram_pex(self, pins, model_name): + self.sf.write("X{0} ".format(model_name)) + for pin in pins: + self.sf.write("{0} ".format(pin)) + for bank in range(OPTS.num_banks): + for row in range(OPTS.num_words): + for col in range(OPTS.word_size): + self.sf.write("bitcell_Q_b{0}_r{1}_c{2} ".format(bank,row,col)) + self.sf.write("bitcell_Q_bar_b{0}_r{1}_c{2} ".format(bank,row,col)) + for col in range(OPTS.word_size): + if OPTS.num_banks == 1: + self.sf.write("bl_{2} ".format(bank, row,col)) + self.sf.write("br_{2} ".format(bank, row,col)) + else: + self.sf.write("bl{0}_{2} ".format(bank, row,col)) + self.sf.write("br{0}_{2} ".format(bank, row,col)) + self.sf.write("s_en{0} ".format(bank)) + self.sf.write("{0}\n".format(model_name)) def create_inverter(self, size=1, beta=2.5): """ Generates inverter for the top level signals (only for sim purposes) """ diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index 5fc510b7..dfe96697 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -115,8 +115,12 @@ class sram_base(design, verilog, lef): self.add_layout_pin_rect_center("bitcell_Q_b{0}_r{1}_c{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , storage_layer_name, Q) self.add_layout_pin_rect_center("bitcell_Q_bar_b{0}_r{1}_c{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)), storage_layer_name, Q_bar) - self.add_layout_pin_rect_center("bl_b{0}_{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , bitline_layer_name, bl) - self.add_layout_pin_rect_center("br_b{0}_{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)), bitline_layer_name, br) + if OPTS.num_banks == 1: + self.add_layout_pin_rect_center("bl_{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , bitline_layer_name, bl) + self.add_layout_pin_rect_center("br_{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)), bitline_layer_name, br) + else: + self.add_layout_pin_rect_center("bl{0}_{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , bitline_layer_name, bl) + self.add_layout_pin_rect_center("br{0}_{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)), bitline_layer_name, br) diff --git a/compiler/verify/magic.py b/compiler/verify/magic.py index 29014797..16f37bdc 100644 --- a/compiler/verify/magic.py +++ b/compiler/verify/magic.py @@ -420,8 +420,12 @@ def correct_port(name, output_file_name, ref_file_name): bitcell_list += "bitcell_Q_b{0}_r{1}_c{2} ".format(bank, row,col) bitcell_list += "bitcell_Q_bar_b{0}_r{1}_c{2} ".format(bank, row,col) for col in range(OPTS.word_size): - bitcell_list += "bl_b{0}_c{2} ".format(bank, row,col) - bitcell_list += "br_b{0}_c{2} ".format(bank, row,col) + if OPTS.num_banks == 1: + bitcell_list += "bl_{2} ".format(bank, row,col) + bitcell_list += "br_{2} ".format(bank, row,col) + else: + bitcell_list += "bl{0}_{2} ".format(bank, row,col) + bitcell_list += "br{0}_{2} ".format(bank, row,col) bitcell_list += "\n" control_list = "+ " From 1062cbfd7f6f01d75d42f65116a0ef05cc527f1c Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Fri, 24 Jan 2020 10:24:29 +0000 Subject: [PATCH 12/31] begin fixes to pbitcell, prepare multibank pex --- compiler/base/geometry.py | 24 ++++++++++------- compiler/bitcells/bitcell_base.py | 44 ++++++++++++++++++++++--------- compiler/sram/sram_base.py | 36 +++++++++++++++---------- 3 files changed, 67 insertions(+), 37 deletions(-) diff --git a/compiler/base/geometry.py b/compiler/base/geometry.py index 0fef7b72..175ec0d3 100644 --- a/compiler/base/geometry.py +++ b/compiler/base/geometry.py @@ -321,7 +321,7 @@ class instance(geometry): cell_paths.append(copy.copy(path)) normalized_storage_nets = node.mod.get_normalized_storage_nets_offset() - normalized_bitline_nets = node.mod.get_normalized_bitline_offset() + (normalized_bl_offsets, normalized_br_offsets) = node.mod.get_normalized_bitline_offset() Q_x = normalized_storage_nets[0][0] Q_y = normalized_storage_nets[0][1] @@ -329,22 +329,26 @@ class instance(geometry): Q_bar_x = normalized_storage_nets[1][0] Q_bar_y = normalized_storage_nets[1][1] - bl_x = normalized_bitline_nets[0][0] - bl_y = normalized_bitline_nets[0][1] - - br_x = normalized_bitline_nets[1][0] - br_y = normalized_bitline_nets[1][1] if node.mirror == 'MX': Q_y = -1 * Q_y Q_bar_y = -1 * Q_bar_y - bl_y = -1 * bl_y - br_y = -1 * br_y + for pair in range(len(normalized_bl_offsets)): + for offset in range(len(offset)): + normalized_bl_offsets[pair][offset] = -1 * normalized_bl_offsets[pair][offset] + + for pair in range(len(normalized_br_offsets)): + for offset in range(len(offset)): + normalized_br_offsets[pair][offset] = -1 * normalized_br_offsets[pair][offset] + Q_offsets.append([Q_x, Q_y]) Q_bar_offsets.append([Q_bar_x, Q_bar_y]) - bl_offsets.append([bl_x, bl_y]) - br_offsets.append([br_x, br_y]) + + for offset in bl_offset: + bl_offsets.append(offset) + for offset in br.offset: + br_offsets.append(offset) elif node.mod.insts is not []: for instance in node.mod.insts: diff --git a/compiler/bitcells/bitcell_base.py b/compiler/bitcells/bitcell_base.py index f0f562c6..069f8f6c 100644 --- a/compiler/bitcells/bitcell_base.py +++ b/compiler/bitcells/bitcell_base.py @@ -100,21 +100,39 @@ class bitcell_base(design.design): return(self.storage_net_offsets) def get_bitline_offset(self): - self.bitline_names = ["bl", "br"] - found_bitlines = [] - self.bitline_offsets = [] - for i in range(len(self.bitline_names)): + + bl_names = self.get_all_bl_names() + br_names = self.get_all_br_names() + + found_bl = [] + found_br = [] + + self.bl_offsets = [] + self.br_offsets = [] + + for i in range(len(bl_names)): for text in self.gds.getTexts(layer["metal2"]): - if not self.bitline_names[i] in found_bitlines: - if self.bitline_names[i] == text.textString.rstrip('\x00'): - self.bitline_offsets.append(text.coordinates[0]) - found_bitlines.append(self.bitline_names[i]) + if not bl_names[i] in found_bl: + if bl_names[i] == text.textString.rstrip('\x00'): + self.bl_offsets.append(text.coordinates[0]) + found_bl.append(bl_names[i]) continue - - for i in range(len(self.bitline_offsets)): - self.bitline_offsets[i] = tuple([self.gds.info["units"][0] * x for x in self.bitline_offsets[i]]) - - return(self.bitline_offsets) + + for i in range(len(br_names)): + for text in self.gds.getTexts(layer["metal2"]): + if not br_names[i] in found_br: + if br_names[i] == text.textString.rstrip('\x00'): + self.br_offsets.append(text.coordinates[0]) + found_br.append(br_names[i]) + continue + + for i in range(len(self.bl_offsets)): + self.bl_offsets[i] = tuple([self.gds.info["units"][0] * x for x in self.bl_offsets[i]]) + + for i in range(len(self.br_offsets)): + self.br_offsets[i] = tuple([self.gds.info["units"][0] * x for x in self.br_offsets[i]]) + + return(self.bl_offsets, self.br_offsets) def get_normalized_storage_nets_offset(self): """ diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index dfe96697..762295d4 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -104,23 +104,31 @@ class sram_base(design, verilog, lef): storage_layer_name = "metal1" bitline_layer_name = "metal2" - - for i in range(0,len(bank_offset)): - Q = [bank_offset[i][0] + Q_offset[i][0], bank_offset[i][1] + Q_offset[i][1]] - Q_bar = [bank_offset[i][0] + Q_bar_offset[i][0], bank_offset[i][1] + Q_bar_offset[i][1]] - bl = [bank_offset[i][0] + bl_offsets[i][0], bank_offset[i][1] + bl_offsets[i][1]] - br = [bank_offset[i][0] + br_offsets[i][0], bank_offset[i][1] + br_offsets[i][1]] + Q = [bank_offset[bank_num][0] + Q_offset[bank_num][0], bank_offset[bank_num][1] + Q_offset[bank_num][1]] + Q_bar = [bank_offset[bank_num][0] + Q_bar_offset[bank_num][0], bank_offset[bank_num][1] + Q_bar_offset[bank_num][1]] + + bl = [] + br = [] - self.add_layout_pin_rect_center("bitcell_Q_b{0}_r{1}_c{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , storage_layer_name, Q) - self.add_layout_pin_rect_center("bitcell_Q_bar_b{0}_r{1}_c{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)), storage_layer_name, Q_bar) + for i in range(len(bl_offsets)): + bl.append([bank_offset[bank_num][1] + bl_offsets[bank_num][2*(i)], bank_offset[bank_num][1] + bl_offsets[bank_num][2*(i)+1]]) - if OPTS.num_banks == 1: + for i in range(len(br_offsets)): + br.append([bank_offset[bank_num][1] + br_offsets[bank_num][2*(i)], bank_offset[bank_num][1] + br_offsets[bank_num][2*(i)+1]]) + + self.add_layout_pin_rect_center("bitcell_Q_b{0}_r{1}_c{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , storage_layer_name, Q) + self.add_layout_pin_rect_center("bitcell_Q_bar_b{0}_r{1}_c{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)), storage_layer_name, Q_bar) + + if OPTS.num_banks == 1: + for i in range(len(bl_offsets)): self.add_layout_pin_rect_center("bl_{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , bitline_layer_name, bl) + + for i in range(len(br_offsets)): self.add_layout_pin_rect_center("br_{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)), bitline_layer_name, br) - else: - self.add_layout_pin_rect_center("bl{0}_{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , bitline_layer_name, bl) - self.add_layout_pin_rect_center("br{0}_{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)), bitline_layer_name, br) + else: + self.add_layout_pin_rect_center("bl{0}_{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , bitline_layer_name, bl) + self.add_layout_pin_rect_center("br{0}_{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)), bitline_layer_name, br) @@ -178,8 +186,8 @@ class sram_base(design, verilog, lef): highest_coord = self.find_highest_coords() self.width = highest_coord[0] self.height = highest_coord[1] - - self.add_global_pex_labels() + if OPTS.use_pex: + self.add_global_pex_labels() start_time = datetime.now() # We only enable final verification if we have routed the design From d42cd9a281f0f1f96f3dc9a5979e882d1343c2be Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Mon, 27 Jan 2020 10:03:31 +0000 Subject: [PATCH 13/31] pbitcell working with bitline adjustments --- compiler/base/geometry.py | 18 ++++++------ compiler/characterizer/stimuli.py | 4 --- compiler/sram/sram_base.py | 48 +++++++++++++++++-------------- compiler/verify/magic.py | 6 +--- 4 files changed, 37 insertions(+), 39 deletions(-) diff --git a/compiler/base/geometry.py b/compiler/base/geometry.py index 175ec0d3..3b2eb2d3 100644 --- a/compiler/base/geometry.py +++ b/compiler/base/geometry.py @@ -333,22 +333,22 @@ class instance(geometry): if node.mirror == 'MX': Q_y = -1 * Q_y Q_bar_y = -1 * Q_bar_y + for pair in range(len(normalized_bl_offsets)): - for offset in range(len(offset)): - normalized_bl_offsets[pair][offset] = -1 * normalized_bl_offsets[pair][offset] + normalized_bl_offsets[pair] = (normalized_bl_offsets[pair][0], + -1 * normalized_bl_offsets[pair][1]) for pair in range(len(normalized_br_offsets)): - for offset in range(len(offset)): - normalized_br_offsets[pair][offset] = -1 * normalized_br_offsets[pair][offset] + normalized_br_offsets[pair] = (normalized_br_offsets[pair][0], + -1 * normalized_br_offsets[pair][1]) Q_offsets.append([Q_x, Q_y]) Q_bar_offsets.append([Q_bar_x, Q_bar_y]) - for offset in bl_offset: - bl_offsets.append(offset) - for offset in br.offset: - br_offsets.append(offset) + + bl_offsets.append(normalized_bl_offsets) + br_offsets.append(normalized_br_offsets) elif node.mod.insts is not []: for instance in node.mod.insts: @@ -360,7 +360,7 @@ class instance(geometry): vector_spaces = self.apply_path_transform(path) origin = vector_spaces[2] origin_offsets.append([origin[0], origin[1]]) - + return(origin_offsets, Q_offsets, Q_bar_offsets, bl_offsets, br_offsets) def __str__(self): diff --git a/compiler/characterizer/stimuli.py b/compiler/characterizer/stimuli.py index f413d97b..b4cd00f4 100644 --- a/compiler/characterizer/stimuli.py +++ b/compiler/characterizer/stimuli.py @@ -63,10 +63,6 @@ class stimuli(): self.sf.write("bitcell_Q_b{0}_r{1}_c{2} ".format(bank,row,col)) self.sf.write("bitcell_Q_bar_b{0}_r{1}_c{2} ".format(bank,row,col)) for col in range(OPTS.word_size): - if OPTS.num_banks == 1: - self.sf.write("bl_{2} ".format(bank, row,col)) - self.sf.write("br_{2} ".format(bank, row,col)) - else: self.sf.write("bl{0}_{2} ".format(bank, row,col)) self.sf.write("br{0}_{2} ".format(bank, row,col)) diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index 762295d4..2c66924a 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -19,6 +19,7 @@ from verilog import verilog from lef import lef from sram_factory import factory from tech import drc +import numpy as np import logical_effort class sram_base(design, verilog, lef): @@ -102,33 +103,38 @@ class sram_base(design, verilog, lef): bl_offsets = pex_offsets[3] br_offsets = pex_offsets[4] - storage_layer_name = "metal1" - bitline_layer_name = "metal2" - - Q = [bank_offset[bank_num][0] + Q_offset[bank_num][0], bank_offset[bank_num][1] + Q_offset[bank_num][1]] - Q_bar = [bank_offset[bank_num][0] + Q_bar_offset[bank_num][0], bank_offset[bank_num][1] + Q_bar_offset[bank_num][1]] - bl = [] br = [] - for i in range(len(bl_offsets)): - bl.append([bank_offset[bank_num][1] + bl_offsets[bank_num][2*(i)], bank_offset[bank_num][1] + bl_offsets[bank_num][2*(i)+1]]) + storage_layer_name = "metal1" + bitline_layer_name = "metal2" + + for cell in range(len(bank_offset)): + Q = [bank_offset[cell][0] + Q_offset[cell][0], bank_offset[cell][1] + Q_offset[cell][1]] + Q_bar = [bank_offset[cell][0] + Q_bar_offset[cell][0], bank_offset[cell][1] + Q_bar_offset[cell][1]] - for i in range(len(br_offsets)): - br.append([bank_offset[bank_num][1] + br_offsets[bank_num][2*(i)], bank_offset[bank_num][1] + br_offsets[bank_num][2*(i)+1]]) + self.add_layout_pin_rect_center("bitcell_Q_b{0}_r{1}_c{2}".format(bank_num, cell % OPTS.num_words, int(cell / OPTS.num_words)) , storage_layer_name, Q) + self.add_layout_pin_rect_center("bitcell_Q_bar_b{0}_r{1}_c{2}".format(bank_num, cell % OPTS.num_words, int(cell / OPTS.num_words)), storage_layer_name, Q_bar) + + for bitline in range(len(bl_offsets[cell])): + bitline_location = [float(bank_offset[cell][0]) + bl_offsets[cell][bitline][0], float(bank_offset[cell][1]) + bl_offsets[cell][bitline][1]] + bl.append(bitline_location) - self.add_layout_pin_rect_center("bitcell_Q_b{0}_r{1}_c{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , storage_layer_name, Q) - self.add_layout_pin_rect_center("bitcell_Q_bar_b{0}_r{1}_c{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)), storage_layer_name, Q_bar) + for bitline in range(len(br_offsets[0])): + bitline_location = [float(bank_offset[cell][0]) + br_offsets[cell][bitline][0], float(bank_offset[cell][1]) + br_offsets[cell][bitline][1]] + br.append(bitline_location) + + for col in range(len(bl)): + if OPTS.num_banks == 1: + self.add_layout_pin_rect_center("bl0_{0}".format(int(col / OPTS.num_words)), bitline_layer_name, bl[col]) + else: + self.add_layout_pin_rect_center("bl{0}_{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , bitline_layer_name, bl) - if OPTS.num_banks == 1: - for i in range(len(bl_offsets)): - self.add_layout_pin_rect_center("bl_{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , bitline_layer_name, bl) - - for i in range(len(br_offsets)): - self.add_layout_pin_rect_center("br_{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)), bitline_layer_name, br) - else: - self.add_layout_pin_rect_center("bl{0}_{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , bitline_layer_name, bl) - self.add_layout_pin_rect_center("br{0}_{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)), bitline_layer_name, br) + for col in range(len(br)): + if OPTS.num_banks == 1: + self.add_layout_pin_rect_center("br0_{0}".format(int(col / OPTS.num_words)), bitline_layer_name, br[col]) + else: + self.add_layout_pin_rect_center("br{0}_{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , bitline_layer_name, br) diff --git a/compiler/verify/magic.py b/compiler/verify/magic.py index 16f37bdc..d81255b6 100644 --- a/compiler/verify/magic.py +++ b/compiler/verify/magic.py @@ -420,12 +420,8 @@ def correct_port(name, output_file_name, ref_file_name): bitcell_list += "bitcell_Q_b{0}_r{1}_c{2} ".format(bank, row,col) bitcell_list += "bitcell_Q_bar_b{0}_r{1}_c{2} ".format(bank, row,col) for col in range(OPTS.word_size): - if OPTS.num_banks == 1: - bitcell_list += "bl_{2} ".format(bank, row,col) - bitcell_list += "br_{2} ".format(bank, row,col) - else: bitcell_list += "bl{0}_{2} ".format(bank, row,col) - bitcell_list += "br{0}_{2} ".format(bank, row,col) + bitcell_list += "br{0}_{2} ".format(bank, row,col) bitcell_list += "\n" control_list = "+ " From 1a97dfc63e29b52db7ebf579c1c1c2eefaea97c0 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Mon, 27 Jan 2020 11:50:43 +0000 Subject: [PATCH 14/31] syncronize bitline naming convention betwen bitcell and pbitcell --- compiler/characterizer/delay.py | 37 ++++++++++++++++++++----------- compiler/characterizer/stimuli.py | 5 +++-- compiler/sram/sram_base.py | 11 +++------ compiler/verify/magic.py | 8 +++---- 4 files changed, 34 insertions(+), 27 deletions(-) diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index 6ec3ae8a..36965f4d 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -130,19 +130,18 @@ class delay(simulation): """ self.bitline_volt_meas = [] - self.bitline_volt_meas.append(voltage_at_measure("v_bl_READ_ZERO", - self.bl_name)) + self.bl_name)) self.bitline_volt_meas[-1].meta_str = sram_op.READ_ZERO self.bitline_volt_meas.append(voltage_at_measure("v_br_READ_ZERO", - self.br_name)) + self.br_name)) self.bitline_volt_meas[-1].meta_str = sram_op.READ_ZERO self.bitline_volt_meas.append(voltage_at_measure("v_bl_READ_ONE", - self.bl_name)) + self.bl_name)) self.bitline_volt_meas[-1].meta_str = sram_op.READ_ONE self.bitline_volt_meas.append(voltage_at_measure("v_br_READ_ONE", - self.br_name)) + self.br_name)) self.bitline_volt_meas[-1].meta_str = sram_op.READ_ONE return self.bitline_volt_meas @@ -264,14 +263,26 @@ class delay(simulation): """Sets important names for characterization such as Sense amp enable and internal bit nets.""" port = self.read_ports[0] - self.graph.get_all_paths('{}{}'.format("clk", port), - '{}{}_{}'.format(self.dout_name, port, self.probe_data)) - - self.sen_name = self.get_sen_name(self.graph.all_paths) - debug.info(2,"s_en name = {}".format(self.sen_name)) - - self.bl_name,self.br_name = self.get_bl_name(self.graph.all_paths, port) - debug.info(2,"bl name={}, br name={}".format(self.bl_name,self.br_name)) + if not OPTS.use_pex: + self.graph.get_all_paths('{}{}'.format("clk", port), + '{}{}_{}'.format(self.dout_name, port, self.probe_data)) + + self.sen_name = self.get_sen_name(self.graph.all_paths) + debug.info(2,"s_en name = {}".format(self.sen_name)) + + self.bl_name,self.br_name = self.get_bl_name(self.graph.all_paths, port) + debug.info(2,"bl name={}, br name={}".format(self.bl_name,self.br_name)) + else: + self.graph.get_all_paths('{}{}'.format("clk", port), + '{}{}_{}'.format(self.dout_name, port, self.probe_data)) + + self.sen_name = self.get_sen_name(self.graph.all_paths) + debug.info(2,"s_en name = {}".format(self.sen_name)) + + + self.bl_name = "bl{0}_{1}".format(port, OPTS.word_size-1) + self.br_name = "br{0}_{1}".format(port, OPTS.word_size-1) + debug.info(2,"bl name={}, br name={}".format(self.bl_name,self.br_name)) def get_sen_name(self, paths): """ diff --git a/compiler/characterizer/stimuli.py b/compiler/characterizer/stimuli.py index b4cd00f4..198dacdd 100644 --- a/compiler/characterizer/stimuli.py +++ b/compiler/characterizer/stimuli.py @@ -63,8 +63,9 @@ class stimuli(): self.sf.write("bitcell_Q_b{0}_r{1}_c{2} ".format(bank,row,col)) self.sf.write("bitcell_Q_bar_b{0}_r{1}_c{2} ".format(bank,row,col)) for col in range(OPTS.word_size): - self.sf.write("bl{0}_{2} ".format(bank, row,col)) - self.sf.write("br{0}_{2} ".format(bank, row,col)) + self.sf.write("bl{0}_{2} ".format(bank, row, col)) + self.sf.write("br{0}_{2} ".format(bank, row, col)) + self.sf.write("s_en{0} ".format(bank)) self.sf.write("{0}\n".format(model_name)) diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index 2c66924a..3479957b 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -125,16 +125,11 @@ class sram_base(design, verilog, lef): br.append(bitline_location) for col in range(len(bl)): - if OPTS.num_banks == 1: - self.add_layout_pin_rect_center("bl0_{0}".format(int(col / OPTS.num_words)), bitline_layer_name, bl[col]) - else: - self.add_layout_pin_rect_center("bl{0}_{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , bitline_layer_name, bl) + self.add_layout_pin_rect_center("bl{0}_{1}".format(bank_num, int(col / OPTS.num_words)), bitline_layer_name, bl[col]) for col in range(len(br)): - if OPTS.num_banks == 1: - self.add_layout_pin_rect_center("br0_{0}".format(int(col / OPTS.num_words)), bitline_layer_name, br[col]) - else: - self.add_layout_pin_rect_center("br{0}_{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , bitline_layer_name, br) + self.add_layout_pin_rect_center("br{0}_{1}".format(bank_num, int(col / OPTS.num_words)), bitline_layer_name, br[col]) + diff --git a/compiler/verify/magic.py b/compiler/verify/magic.py index d81255b6..93472e2a 100644 --- a/compiler/verify/magic.py +++ b/compiler/verify/magic.py @@ -417,11 +417,11 @@ def correct_port(name, output_file_name, ref_file_name): for bank in range(OPTS.num_banks): for row in range(OPTS.num_words): for col in range(OPTS.word_size): - bitcell_list += "bitcell_Q_b{0}_r{1}_c{2} ".format(bank, row,col) - bitcell_list += "bitcell_Q_bar_b{0}_r{1}_c{2} ".format(bank, row,col) + bitcell_list += "bitcell_Q_b{0}_r{1}_c{2} ".format(bank, row, col) + bitcell_list += "bitcell_Q_bar_b{0}_r{1}_c{2} ".format(bank, row, col) for col in range(OPTS.word_size): - bitcell_list += "bl{0}_{2} ".format(bank, row,col) - bitcell_list += "br{0}_{2} ".format(bank, row,col) + bitcell_list += "bl{0}_{2} ".format(bank, row, col) + bitcell_list += "br{0}_{2} ".format(bank, row, col) bitcell_list += "\n" control_list = "+ " From 30604fb093dc752479d03124031ad8ef2874833e Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Tue, 28 Jan 2020 00:28:55 +0000 Subject: [PATCH 15/31] add multiport support for pex labels --- compiler/base/geometry.py | 44 +++++++++++++----- compiler/bitcells/bitcell_base.py | 3 +- .../example_config_1w_1r_scn4m_subm.py | 4 +- compiler/sram/sram_base.py | 38 +++++++++------ technology/scn4m_subm/gds_lib/cell_1w_1r.gds | Bin 8192 -> 6406 bytes 5 files changed, 59 insertions(+), 30 deletions(-) diff --git a/compiler/base/geometry.py b/compiler/base/geometry.py index 3b2eb2d3..02b100ad 100644 --- a/compiler/base/geometry.py +++ b/compiler/base/geometry.py @@ -136,8 +136,7 @@ class geometry: def cy(self): """ Return the center y """ return 0.5 * (self.boundary[0].y + self.boundary[1].y) - - + class instance(geometry): """ An instance of an instance/module with a specified location and @@ -306,29 +305,47 @@ class instance(geometry): return (uVector, vVector, origin) def reverse_transformation_bitcell(self, cell_name): - path = [] - cell_paths = [] - origin_offsets = [] - Q_offsets = [] - Q_bar_offsets = [] - bl_offsets = [] - br_offsets = [] + path = [] # path currently follwed in bitcell search + cell_paths = [] # saved paths to bitcells + origin_offsets = [] # cell to bank offset + Q_offsets = [] # Q to cell offet + Q_bar_offsets = [] # Q_bar to cell offset + bl_offsets = [] # bl to cell offset + br_offsets = [] # br to cell offset + bl_meta = [] # bl offset metadata (row,col,name) + br_meta = [] #br offset metadata (row,col,name) def walk_subtree(node): path.append(node) if node.mod.name == cell_name: cell_paths.append(copy.copy(path)) + + inst_name = path[-1].name + # get the row and col names from the path + row = int(path[-1].name.split('_')[-2][1:]) + col = int(path[-1].name.split('_')[-1][1:]) + + cell_bl_meta = [] + cell_br_meta = [] + normalized_storage_nets = node.mod.get_normalized_storage_nets_offset() - (normalized_bl_offsets, normalized_br_offsets) = node.mod.get_normalized_bitline_offset() + (normalized_bl_offsets, normalized_br_offsets, bl_names, br_names) = node.mod.get_normalized_bitline_offset() + + for offset in range(len(normalized_bl_offsets)): + for port in range(len(bl_names)): + cell_bl_meta.append([bl_names[offset], row, col, port]) + + for offset in range(len(normalized_br_offsets)): + for port in range(len(br_names)): + cell_br_meta.append([br_names[offset], row, col, port]) Q_x = normalized_storage_nets[0][0] Q_y = normalized_storage_nets[0][1] Q_bar_x = normalized_storage_nets[1][0] Q_bar_y = normalized_storage_nets[1][1] - if node.mirror == 'MX': Q_y = -1 * Q_y @@ -350,6 +367,9 @@ class instance(geometry): bl_offsets.append(normalized_bl_offsets) br_offsets.append(normalized_br_offsets) + bl_meta.append(cell_bl_meta) + br_meta.append(cell_br_meta) + elif node.mod.insts is not []: for instance in node.mod.insts: walk_subtree(instance) @@ -361,7 +381,7 @@ class instance(geometry): origin = vector_spaces[2] origin_offsets.append([origin[0], origin[1]]) - return(origin_offsets, Q_offsets, Q_bar_offsets, bl_offsets, br_offsets) + return(origin_offsets, Q_offsets, Q_bar_offsets, bl_offsets, br_offsets, bl_meta, br_meta) def __str__(self): """ override print function output """ diff --git a/compiler/bitcells/bitcell_base.py b/compiler/bitcells/bitcell_base.py index 069f8f6c..58f7bdcb 100644 --- a/compiler/bitcells/bitcell_base.py +++ b/compiler/bitcells/bitcell_base.py @@ -116,6 +116,7 @@ class bitcell_base(design.design): if bl_names[i] == text.textString.rstrip('\x00'): self.bl_offsets.append(text.coordinates[0]) found_bl.append(bl_names[i]) + continue for i in range(len(br_names)): @@ -132,7 +133,7 @@ class bitcell_base(design.design): for i in range(len(self.br_offsets)): self.br_offsets[i] = tuple([self.gds.info["units"][0] * x for x in self.br_offsets[i]]) - return(self.bl_offsets, self.br_offsets) + return(self.bl_offsets, self.br_offsets, found_bl, found_br) def get_normalized_storage_nets_offset(self): """ diff --git a/compiler/example_configs/example_config_1w_1r_scn4m_subm.py b/compiler/example_configs/example_config_1w_1r_scn4m_subm.py index 4b6584d4..fde94de0 100644 --- a/compiler/example_configs/example_config_1w_1r_scn4m_subm.py +++ b/compiler/example_configs/example_config_1w_1r_scn4m_subm.py @@ -1,9 +1,9 @@ word_size = 2 num_words = 16 -num_rw_ports = 1 +num_rw_ports = 0 num_r_ports = 1 -num_w_ports = 0 +num_w_ports = 1 tech_name = "scn4m_subm" process_corners = ["TT"] diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index 3479957b..8d4bc330 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -95,13 +95,15 @@ class sram_base(design, verilog, lef): # add pex labels for bitcells for bank_num in range(len(self.bank_insts)): bank = self.bank_insts[bank_num] - pex_offsets = bank.reverse_transformation_bitcell(bank.mod.bitcell.name) + pex_data = bank.reverse_transformation_bitcell(bank.mod.bitcell.name) - bank_offset = pex_offsets[0] # offset bank relative to sram - Q_offset = pex_offsets[1] # offset of storage relative to bank - Q_bar_offset = pex_offsets[2] # offset of storage relative to bank - bl_offsets = pex_offsets[3] - br_offsets = pex_offsets[4] + bank_offset = pex_data[0] # offset bank relative to sram + Q_offset = pex_data[1] # offset of storage relative to bank + Q_bar_offset = pex_data[2] # offset of storage relative to bank + bl_offsets = pex_data[3] + br_offsets = pex_data[4] + bl_meta = pex_data[5] + br_meta = pex_data[6] bl = [] br = [] @@ -116,20 +118,26 @@ class sram_base(design, verilog, lef): self.add_layout_pin_rect_center("bitcell_Q_b{0}_r{1}_c{2}".format(bank_num, cell % OPTS.num_words, int(cell / OPTS.num_words)) , storage_layer_name, Q) self.add_layout_pin_rect_center("bitcell_Q_bar_b{0}_r{1}_c{2}".format(bank_num, cell % OPTS.num_words, int(cell / OPTS.num_words)), storage_layer_name, Q_bar) + for cell in range(len(bl_offsets)): + col = bl_meta[cell][0][2] for bitline in range(len(bl_offsets[cell])): bitline_location = [float(bank_offset[cell][0]) + bl_offsets[cell][bitline][0], float(bank_offset[cell][1]) + bl_offsets[cell][bitline][1]] - bl.append(bitline_location) + bl.append([bitline_location, bl_meta[cell][bitline][3], col]) - for bitline in range(len(br_offsets[0])): + for cell in range(len(br_offsets)): + col = br_meta[cell][0][2] + for bitline in range(len(br_offsets[cell])): bitline_location = [float(bank_offset[cell][0]) + br_offsets[cell][bitline][0], float(bank_offset[cell][1]) + br_offsets[cell][bitline][1]] - br.append(bitline_location) - - for col in range(len(bl)): - self.add_layout_pin_rect_center("bl{0}_{1}".format(bank_num, int(col / OPTS.num_words)), bitline_layer_name, bl[col]) + br.append([bitline_location, br_meta[cell][bitline][3], col]) - for col in range(len(br)): - self.add_layout_pin_rect_center("br{0}_{1}".format(bank_num, int(col / OPTS.num_words)), bitline_layer_name, br[col]) - + + + + for i in range(len(bl)): + self.add_layout_pin_rect_center("bl{0}_{1}".format(bl[i][1], bl[i][2]), bitline_layer_name, bl[i][0]) + + for i in range(len(br)): + self.add_layout_pin_rect_center("br{0}_{1}".format(br[i][1], br[i][2]), bitline_layer_name, br[i][0]) diff --git a/technology/scn4m_subm/gds_lib/cell_1w_1r.gds b/technology/scn4m_subm/gds_lib/cell_1w_1r.gds index 782c43dc67499f61fd6df7d7481bc6a0311a0b32..06f79ba5d4a3d86bf948a0040ea1f6fd7fbefb55 100644 GIT binary patch literal 6406 zcmbW5J&aXF7=}OYE_WAPmW%SYvdSudEAq1oLBK*Wu^^$*#DdtcB1Q^g%oZ-?mfBI0 z*lZ^yC8d?2q_ni8q_p&X?wmJg?!|9RJjvbX?mP3&H}lP$nR9LoV-Pd3ylW6!u@Fb} z-zZk&VeE=yL*|z8ME+c7O8OFIR8<@!PBGpFg{}^Xu1N#q#ck zdsw??=Oc#u25~lqi-U+bH=5C3T_;{eoL%er@#CVKDxWEo4^h{I2MUb|8HZmK-> z@4Kmmq&7zPd!GLy0^L-3>L)&a;+y!;&6a=ZdGRg3?1>NEZ29RYYZt#sKRm9kJnjG7 ze2H~pwI^+%o9avIr+vmwU6a0}o6=K1ai~jtletGXrKf)KOkHA|dsj>TP3g6NtzJI| zmFp`nBMxcJnpYo2pqtWD|J;j+w;x69+32~f^@wh&JoPV*if{i;PkiWR%TH`R)HUnx zU3nURh&i4Wau`H4fWiEr-N zDDh3{b^kBa_s@Z~lDjv5@5#Q8ZYsB_|HzLKXEcAT9TOkADLwTcI$F*y{G4HK2c7o1 z^3>0mkKc$`*zU<%KsQyM`uDyn=PZ8CTepKwyIpzeCr{L)pC)mg*RDMEGe_i}xF&On zZc0!6^pA5Ezezjjru5WL|L{@QWE>t>SDyNrXMD_?$vmQ)(o_FCPfOm&8F3*WbW?iM z&%EI^`R;b1^roM&vtO9x9iJ(^>1W);G-(IFIW_)^_5DYTQ`;q9=9y86ZA!1>Px$8_ ztMBug@712~NkcbPp8CgQmY;oub|5}@S`-~@dJPSbXC3I7I>gO37 zA8|~4=;oCFQk{Rs>*og3&kg3(^TTU?_HE|T^uBLS?cWpr!R@lw&%Erpyb^(K>MW?o zKjA-pv-sF6IWr(WbhG8>nT@=0_L}4k-E8IW*zMxu`4KVtn?PwBvTW@}{4@6W^pAw+p4Ge(rhBNxUZg zM>nOXe%{eEzhl2iJLqO>{_*gkuF1OLyQ%MKeELb>>knRZvo-!*s>fV&UYN9nZc0z% zlV5zSUlU)K_c2?3_ASmz=Fj9TKsTkQ@pd%#<^D10Ke{PB^)qHZ z)HUnxU3u!~+@%h`9hvyiP3fthc_weu&tK@|uPaae#366>?+@e+-E8GAbdhWB6_Y%2 znbOnv)MKsTH)o%sMwrrT|K)oB$5YqE!@iGhsyy}6XD;^@;zKu8ocjN5|HX%HYHX>0 zVY~E|^-rH6^M-D=#?SoX<9XTiyqhgQ^UTHkoAevql%Dqg)HbfNeocJnru5qXX+3{< zxR`(QBaMa2)Yq|pq5S@>^Ybvje=qR+H_sjG*J6HYxb;9yH0!B7)%)q*y+%Erxn@>M zd+YyEPwxn7@B1I7+SB^%`=_?}eOLAFPWNx39`75jHx+lH9`6QSz0FoV-hEuJl^6EC e(>G(dH2ktLT2`}mn7yiX=k7O~UClXhHvR$Vczuxo literal 8192 zcmeI0J8T_A6o!u-=lT)HvGZ`8V2H_s7?b#sD8!)vBT+=6p+qzZ;6Mrsp$JGym(Wp0 zqH#w`moBML%9JT7T~MT?uBn!mFP|Oy2L&x|sUOOB}>c ze$#rJ|IE|khxlf9d&J*dPxI4mYUO_5#|N#8segE+?O(3P&q>w%#;&G@c=J)jsXuzOE~ftBXAx(A zRvW}wjl``sp8eAbIJ(X}v8!F$)^Eka>sK zv@WLkX+LogAN4b>xB00xaS$KR(6rv>Coi>!qv|{PP3vOa{;T!;VXj_RZg@-gnOW`8 zx|sS8KPn#hhR%ySJ#w$+dg?!-c;-GNo_m|6-kgYPpPANZ#YW^~hLmuBZOf-$q=19s%()XHDy3>OVD8 zY6gkNZ(iKdcq-RZKV$6NS{Z}1cYL$-2U-_X|JaLCGf2FBkXkm^Q$O{==Q`3}+5xS% zw$n)a)nbzC_JL|Ym_8)P&3oI zn6{twk~oNuoTl|Y|4Lo|&~amqzva81Z(jBR(7IUXf62e}q-&3BPm9mAE~fr^{UV-u zY%+$L>#3h_Tz{wc??0@Ish=7V2fgnwt+)C4RwoYj??0@!`Ds7vz58)&tK1J-7t{9R zW4-ZxnDh9cb+OgYp2PPcFFt5pO#OT}v1WC@qf`ex^cz|iQ$O!*o--ugK4@J`{lxfW z+;9)mdYhkilM52>ywJLs<{yxcXAg;I9-G$1)KA@sgZTLNHm$e$N7Y}}F34KSb2F`r zX@2&2^)qk0hSBcnC#C(+x|sUuqfh+xX}zugtarpgynHj7*4z9%cj^TF z-ZQPY)sMW?2~s!q|EBe}`h^Z^&q2MIJEnCptsg$d9>>sj@tfAgu7AAz{-pJLn%|!~ zrw90ZmcQft7R7#VWi>|5bRKS~8T=TX`C zJ?&ckKI8rE-yQb(d&EnA_I=#P`$*Gz-+pk9fAG^Xmf-B1`nlU9W30JeKhHh>w{90d z#Lrr8;%}~}e#RVg5>jWLscBtI{jaIr#6f(_CDVGFpZ7I;dB|GCx@1}x)BOMA_k=z5 zqu#3h-#2Nzof6uiprvCBG(njd_h)LU<>#3hHN}ShI?<=5nG4->KazNV8dTLr1Q~#w+ zqRO5EAMXRxy4dwM>!IrZ@9Uw~D1KYen)5~fdYF3HhuG7%wxu5S42|c(em(4w>{;Gh rj}PkcNS}RZo$ihe)4JHL$FMk5i3k54RN$Zj2NgJ|z(ECG%?kVt)Hin7 From 6e070925b642691f412d5fc0fcce563edef9cd3f Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Tue, 28 Jan 2020 02:32:34 +0000 Subject: [PATCH 16/31] update magic for multiport --- compiler/characterizer/stimuli.py | 5 +++-- compiler/sram/sram_base.py | 10 ++-------- compiler/verify/magic.py | 1 + 3 files changed, 6 insertions(+), 10 deletions(-) diff --git a/compiler/characterizer/stimuli.py b/compiler/characterizer/stimuli.py index 198dacdd..5e0bd52e 100644 --- a/compiler/characterizer/stimuli.py +++ b/compiler/characterizer/stimuli.py @@ -63,8 +63,9 @@ class stimuli(): self.sf.write("bitcell_Q_b{0}_r{1}_c{2} ".format(bank,row,col)) self.sf.write("bitcell_Q_bar_b{0}_r{1}_c{2} ".format(bank,row,col)) for col in range(OPTS.word_size): - self.sf.write("bl{0}_{2} ".format(bank, row, col)) - self.sf.write("br{0}_{2} ".format(bank, row, col)) + for port in range(OPTS.num_r_ports + OPTS.num_w_ports + OPTS.num_rw_ports): + self.sf.write("bl{0}_{2} ".format(port, row, col)) + self.sf.write("br{0}_{2} ".format(port, row, col)) self.sf.write("s_en{0} ".format(bank)) diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index 8d4bc330..bdb84b97 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -128,19 +128,13 @@ class sram_base(design, verilog, lef): col = br_meta[cell][0][2] for bitline in range(len(br_offsets[cell])): bitline_location = [float(bank_offset[cell][0]) + br_offsets[cell][bitline][0], float(bank_offset[cell][1]) + br_offsets[cell][bitline][1]] - br.append([bitline_location, br_meta[cell][bitline][3], col]) - - - + br.append([bitline_location, br_meta[cell][bitline][3], col]) for i in range(len(bl)): self.add_layout_pin_rect_center("bl{0}_{1}".format(bl[i][1], bl[i][2]), bitline_layer_name, bl[i][0]) for i in range(len(br)): - self.add_layout_pin_rect_center("br{0}_{1}".format(br[i][1], br[i][2]), bitline_layer_name, br[i][0]) - - - + self.add_layout_pin_rect_center("br{0}_{1}".format(br[i][1], br[i][2]), bitline_layer_name, br[i][0]) # add pex labels for control logic for i in range (len(self.control_logic_insts)): diff --git a/compiler/verify/magic.py b/compiler/verify/magic.py index 93472e2a..432325ea 100644 --- a/compiler/verify/magic.py +++ b/compiler/verify/magic.py @@ -420,6 +420,7 @@ def correct_port(name, output_file_name, ref_file_name): bitcell_list += "bitcell_Q_b{0}_r{1}_c{2} ".format(bank, row, col) bitcell_list += "bitcell_Q_bar_b{0}_r{1}_c{2} ".format(bank, row, col) for col in range(OPTS.word_size): + for port in range(OPTS.num_r_ports + OPTS.num_w_ports + OPTS.num_rw_ports): bitcell_list += "bl{0}_{2} ".format(bank, row, col) bitcell_list += "br{0}_{2} ".format(bank, row, col) bitcell_list += "\n" From 89688f8ea9a696fc418db45a7c322940de8b17d0 Mon Sep 17 00:00:00 2001 From: jcirimel Date: Mon, 4 May 2020 01:31:51 -0700 Subject: [PATCH 17/31] fix pex for larger memories --- compiler/sram/sram_base.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index bdb84b97..652615dd 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -115,8 +115,8 @@ class sram_base(design, verilog, lef): Q = [bank_offset[cell][0] + Q_offset[cell][0], bank_offset[cell][1] + Q_offset[cell][1]] Q_bar = [bank_offset[cell][0] + Q_bar_offset[cell][0], bank_offset[cell][1] + Q_bar_offset[cell][1]] - self.add_layout_pin_rect_center("bitcell_Q_b{0}_r{1}_c{2}".format(bank_num, cell % OPTS.num_words, int(cell / OPTS.num_words)) , storage_layer_name, Q) - self.add_layout_pin_rect_center("bitcell_Q_bar_b{0}_r{1}_c{2}".format(bank_num, cell % OPTS.num_words, int(cell / OPTS.num_words)), storage_layer_name, Q_bar) + self.add_layout_pin_rect_center("bitcell_Q_b{0}_r{1}_c{2}".format(bank_num, cell % (OPTS.num_words * self.words_per_row), int(cell / (OPTS.num_words / self.words_per_row))) , storage_layer_name, Q) + self.add_layout_pin_rect_center("bitcell_Q_bar_b{0}_r{1}_c{2}".format(bank_num, cell % (OPTS.num_words * self.words_per_row), int(cell / (OPTS.num_words / self.words_per_row))), storage_layer_name, Q_bar) for cell in range(len(bl_offsets)): col = bl_meta[cell][0][2] From 0f9e38881c5736e732df1c8ea83db0b0cd4beaa2 Mon Sep 17 00:00:00 2001 From: jcirimel Date: Mon, 4 May 2020 03:05:33 -0700 Subject: [PATCH 18/31] update stim for large pex layouts --- compiler/characterizer/stimuli.py | 6 +++--- compiler/sram/sram_base.py | 6 +++--- compiler/verify/magic.py | 6 +++--- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/compiler/characterizer/stimuli.py b/compiler/characterizer/stimuli.py index 5e0bd52e..c8ee0492 100644 --- a/compiler/characterizer/stimuli.py +++ b/compiler/characterizer/stimuli.py @@ -58,11 +58,11 @@ class stimuli(): for pin in pins: self.sf.write("{0} ".format(pin)) for bank in range(OPTS.num_banks): - for row in range(OPTS.num_words): - for col in range(OPTS.word_size): + for row in range(int(OPTS.num_words / OPTS.words_per_row)): + for col in range(int(OPTS.word_size * OPTS.words_per_row)): self.sf.write("bitcell_Q_b{0}_r{1}_c{2} ".format(bank,row,col)) self.sf.write("bitcell_Q_bar_b{0}_r{1}_c{2} ".format(bank,row,col)) - for col in range(OPTS.word_size): + for col in range(OPTS.word_size * OPTS.words_per_row): for port in range(OPTS.num_r_ports + OPTS.num_w_ports + OPTS.num_rw_ports): self.sf.write("bl{0}_{2} ".format(port, row, col)) self.sf.write("br{0}_{2} ".format(port, row, col)) diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index 652615dd..3cace3d6 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -114,9 +114,9 @@ class sram_base(design, verilog, lef): for cell in range(len(bank_offset)): Q = [bank_offset[cell][0] + Q_offset[cell][0], bank_offset[cell][1] + Q_offset[cell][1]] Q_bar = [bank_offset[cell][0] + Q_bar_offset[cell][0], bank_offset[cell][1] + Q_bar_offset[cell][1]] - - self.add_layout_pin_rect_center("bitcell_Q_b{0}_r{1}_c{2}".format(bank_num, cell % (OPTS.num_words * self.words_per_row), int(cell / (OPTS.num_words / self.words_per_row))) , storage_layer_name, Q) - self.add_layout_pin_rect_center("bitcell_Q_bar_b{0}_r{1}_c{2}".format(bank_num, cell % (OPTS.num_words * self.words_per_row), int(cell / (OPTS.num_words / self.words_per_row))), storage_layer_name, Q_bar) + OPTS.words_per_row = self.words_per_row + self.add_layout_pin_rect_center("bitcell_Q_b{0}_r{1}_c{2}".format(bank_num, int(cell % (OPTS.num_words / self.words_per_row)), int(cell / (OPTS.word_size * self.words_per_row))) , storage_layer_name, Q) + self.add_layout_pin_rect_center("bitcell_Q_bar_b{0}_r{1}_c{2}".format(bank_num, int(cell % (OPTS.num_words / self.words_per_row)), int(cell / (OPTS.word_size * self.words_per_row))), storage_layer_name, Q_bar) for cell in range(len(bl_offsets)): col = bl_meta[cell][0][2] diff --git a/compiler/verify/magic.py b/compiler/verify/magic.py index 432325ea..de206b87 100644 --- a/compiler/verify/magic.py +++ b/compiler/verify/magic.py @@ -415,11 +415,11 @@ def correct_port(name, output_file_name, ref_file_name): bitcell_list = "+ " for bank in range(OPTS.num_banks): - for row in range(OPTS.num_words): - for col in range(OPTS.word_size): + for row in range(int(OPTS.num_words / OPTS.words_per_row)): + for col in range(int(OPTS.word_size * OPTS.words_per_row)): bitcell_list += "bitcell_Q_b{0}_r{1}_c{2} ".format(bank, row, col) bitcell_list += "bitcell_Q_bar_b{0}_r{1}_c{2} ".format(bank, row, col) - for col in range(OPTS.word_size): + for col in range(OPTS.word_size * OPTS.words_per_row): for port in range(OPTS.num_r_ports + OPTS.num_w_ports + OPTS.num_rw_ports): bitcell_list += "bl{0}_{2} ".format(bank, row, col) bitcell_list += "br{0}_{2} ".format(bank, row, col) From 575278998d42648acc089aa94fa9d7d5b5036bed Mon Sep 17 00:00:00 2001 From: jcirimel Date: Thu, 28 May 2020 23:56:15 -0700 Subject: [PATCH 19/31] write only used bitcells to top level in stim and pex output --- compiler/characterizer/stimuli.py | 18 ++++++++++++------ compiler/verify/magic.py | 13 +++++++------ 2 files changed, 19 insertions(+), 12 deletions(-) diff --git a/compiler/characterizer/stimuli.py b/compiler/characterizer/stimuli.py index c8ee0492..fb2e261d 100644 --- a/compiler/characterizer/stimuli.py +++ b/compiler/characterizer/stimuli.py @@ -58,14 +58,20 @@ class stimuli(): for pin in pins: self.sf.write("{0} ".format(pin)) for bank in range(OPTS.num_banks): - for row in range(int(OPTS.num_words / OPTS.words_per_row)): - for col in range(int(OPTS.word_size * OPTS.words_per_row)): - self.sf.write("bitcell_Q_b{0}_r{1}_c{2} ".format(bank,row,col)) - self.sf.write("bitcell_Q_bar_b{0}_r{1}_c{2} ".format(bank,row,col)) + row = int(OPTS.num_words / OPTS.words_per_row) - 1 + col = int(OPTS.word_size * OPTS.words_per_row) - 1 + self.sf.write("bitcell_Q_b{0}_r{1}_c{2} ".format(bank,row,col)) + self.sf.write("bitcell_Q_bar_b{0}_r{1}_c{2} ".format(bank,row,col)) + # can't add all bitcells to top level due to ngspice max port count of 1005 + # for row in range(int(OPTS.num_words / OPTS.words_per_row)): + # for col in range(int(OPTS.word_size * OPTS.words_per_row)): + # self.sf.write("bitcell_Q_b{0}_r{1}_c{2} ".format(bank,row,col)) + # self.sf.write("bitcell_Q_bar_b{0}_r{1}_c{2} ".format(bank,row,col)) + for bank in range(OPTS.num_banks): for col in range(OPTS.word_size * OPTS.words_per_row): for port in range(OPTS.num_r_ports + OPTS.num_w_ports + OPTS.num_rw_ports): - self.sf.write("bl{0}_{2} ".format(port, row, col)) - self.sf.write("br{0}_{2} ".format(port, row, col)) + self.sf.write("bl{0}_{1} ".format(port, col)) + self.sf.write("br{0}_{1} ".format(port, col)) self.sf.write("s_en{0} ".format(bank)) diff --git a/compiler/verify/magic.py b/compiler/verify/magic.py index de206b87..c2960aa6 100644 --- a/compiler/verify/magic.py +++ b/compiler/verify/magic.py @@ -415,14 +415,15 @@ def correct_port(name, output_file_name, ref_file_name): bitcell_list = "+ " for bank in range(OPTS.num_banks): - for row in range(int(OPTS.num_words / OPTS.words_per_row)): - for col in range(int(OPTS.word_size * OPTS.words_per_row)): - bitcell_list += "bitcell_Q_b{0}_r{1}_c{2} ".format(bank, row, col) - bitcell_list += "bitcell_Q_bar_b{0}_r{1}_c{2} ".format(bank, row, col) + for bank in range(OPTS.num_banks): + row = int(OPTS.num_words / OPTS.words_per_row) - 1 + col = int(OPTS.word_size * OPTS.words_per_row) - 1 + bitcell_list += "bitcell_Q_b{0}_r{1}_c{2} ".format(bank,row,col) + bitcell_list += "bitcell_Q_bar_b{0}_r{1}_c{2} ".format(bank,row,col) for col in range(OPTS.word_size * OPTS.words_per_row): for port in range(OPTS.num_r_ports + OPTS.num_w_ports + OPTS.num_rw_ports): - bitcell_list += "bl{0}_{2} ".format(bank, row, col) - bitcell_list += "br{0}_{2} ".format(bank, row, col) + bitcell_list += "bl{0}_{1} ".format(bank, col) + bitcell_list += "br{0}_{1} ".format(bank, col) bitcell_list += "\n" control_list = "+ " From 1d9296ceb1ab9b5a1d7472657691d66d20535228 Mon Sep 17 00:00:00 2001 From: jcirimel Date: Tue, 21 Jul 2020 11:50:25 -0700 Subject: [PATCH 20/31] fix magic.py conflict --- compiler/verify/magic.py | 18 ------------------ 1 file changed, 18 deletions(-) diff --git a/compiler/verify/magic.py b/compiler/verify/magic.py index 9695591d..1be2f2cd 100644 --- a/compiler/verify/magic.py +++ b/compiler/verify/magic.py @@ -107,7 +107,6 @@ def write_magic_script(cell_name, extract=False, final_verification=False): # f.write(pre + "ext2spice hierarchy on\n") # f.write(pre + "ext2spice scale off\n") # lvs exists in 8.2.79, but be backword compatible for now -<<<<<<< HEAD #f.write(pre+"ext2spice lvs\n") f.write(pre+"ext2spice hierarchy on\n") f.write(pre+"ext2spice format ngspice\n") @@ -123,23 +122,6 @@ def write_magic_script(cell_name, extract=False, final_verification=False): # but they all seem compatible enough. f.write(pre+"ext2spice format ngspice\n") f.write(pre+"ext2spice {}\n".format(cell_name)) -======= - # f.write(pre + "ext2spice lvs\n") - f.write(pre + "ext2spice hierarchy on\n") - f.write(pre + "ext2spice format ngspice\n") - f.write(pre + "ext2spice cthresh infinite\n") - f.write(pre + "ext2spice rthresh infinite\n") - f.write(pre + "ext2spice renumber off\n") - f.write(pre + "ext2spice scale off\n") - f.write(pre + "ext2spice blackbox on\n") - f.write(pre + "ext2spice subcircuit top auto\n") - f.write(pre + "ext2spice global off\n") - - # Can choose hspice, ngspice, or spice3, - # but they all seem compatible enough. - #f.write(pre + "ext2spice format ngspice\n") - f.write(pre + "ext2spice {}\n".format(cell_name)) ->>>>>>> dev f.write("quit -noprompt\n") f.write("EOF\n") From 3221b4ec5724c50419784723bb0e0588118e3503 Mon Sep 17 00:00:00 2001 From: jcirimel Date: Fri, 31 Jul 2020 05:27:19 -0700 Subject: [PATCH 21/31] update to new metal stack names --- compiler/bitcells/bitcell.py | 4 ++-- compiler/bitcells/bitcell_base.py | 6 +++--- compiler/bitcells/pbitcell.py | 18 +++++++++--------- 3 files changed, 14 insertions(+), 14 deletions(-) diff --git a/compiler/bitcells/bitcell.py b/compiler/bitcells/bitcell.py index e91d8c2f..814d9308 100644 --- a/compiler/bitcells/bitcell.py +++ b/compiler/bitcells/bitcell.py @@ -33,7 +33,7 @@ class bitcell(bitcell_base.bitcell_base): props.bitcell.cell_6t.pin.vdd, props.bitcell.cell_6t.pin.gnd] type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"] - storage_nets = ['Q', 'Qbar'] + storage_nets = ['Q', 'Q_bar'] (width, height) = utils.get_libcell_size("cell_6t", GDS["unit"], @@ -51,7 +51,7 @@ class bitcell(bitcell_base.bitcell_base): self.add_pin_types(self.type_list) self.nets_match = self.do_nets_exist(self.storage_nets) - debug.check(OPTS.tech_name != "sky130", "sky130 does not yet support single port cells") +# debug.check(OPTS.tech_name != "sky130", "sky130 does not yet support single port cells") def get_all_wl_names(self): """ Creates a list of all wordline pin names """ diff --git a/compiler/bitcells/bitcell_base.py b/compiler/bitcells/bitcell_base.py index 58f7bdcb..690e98fa 100644 --- a/compiler/bitcells/bitcell_base.py +++ b/compiler/bitcells/bitcell_base.py @@ -89,7 +89,7 @@ class bitcell_base(design.design): if OPTS.bitcell is not "pbitcell": self.storage_net_offsets = [] for i in range(len(self.get_storage_net_names())): - for text in self.gds.getTexts(layer["metal1"]): + for text in self.gds.getTexts(layer["m1"]): if self.storage_nets[i] == text.textString.rstrip('\x00'): self.storage_net_offsets.append(text.coordinates[0]) @@ -111,7 +111,7 @@ class bitcell_base(design.design): self.br_offsets = [] for i in range(len(bl_names)): - for text in self.gds.getTexts(layer["metal2"]): + for text in self.gds.getTexts(layer["m2"]): if not bl_names[i] in found_bl: if bl_names[i] == text.textString.rstrip('\x00'): self.bl_offsets.append(text.coordinates[0]) @@ -120,7 +120,7 @@ class bitcell_base(design.design): continue for i in range(len(br_names)): - for text in self.gds.getTexts(layer["metal2"]): + for text in self.gds.getTexts(layer["m2"]): if not br_names[i] in found_br: if br_names[i] == text.textString.rstrip('\x00'): self.br_offsets.append(text.coordinates[0]) diff --git a/compiler/bitcells/pbitcell.py b/compiler/bitcells/pbitcell.py index 98e477d8..25868df5 100644 --- a/compiler/bitcells/pbitcell.py +++ b/compiler/bitcells/pbitcell.py @@ -401,16 +401,16 @@ class pbitcell(bitcell_base.bitcell_base): gate_offset_left = vector(self.inverter_nmos_left.get_pin("G").rc().x, contact_offset_right.y) self.add_path("poly", [contact_offset_right, gate_offset_left]) - + if OPTS.use_pex: # add labels to cross couple inverter for extracted simulation - contact_offset_left_output = vector(self.inverter_nmos_left.get_pin("D").rc().x \ - + 0.5 * contact.poly.height, - self.cross_couple_upper_ypos) - - contact_offset_right_output = vector(self.inverter_nmos_right.get_pin("S").lc().x \ - - 0.5*contact.poly.height, - self.cross_couple_lower_ypos) - self.add_pex_labels(contact_offset_left_output, contact_offset_right_output) + contact_offset_left_output = vector(self.inverter_nmos_left.get_pin("D").rc().x \ + + 0.5 * contact.poly.height, + self.cross_couple_upper_ypos) + + contact_offset_right_output = vector(self.inverter_nmos_right.get_pin("S").lc().x \ + - 0.5*contact.poly.height, + self.cross_couple_lower_ypos) + self.add_pex_labels(contact_offset_left_output, contact_offset_right_output) def route_rails(self): """ Adds gnd and vdd rails and connects them to the inverters """ From 02e65a00efffeabddd67dc887a971b70c6ae85b7 Mon Sep 17 00:00:00 2001 From: jcirimel Date: Mon, 3 Aug 2020 17:14:34 -0700 Subject: [PATCH 22/31] update pex to work with dev changes --- compiler/characterizer/delay.py | 8 ++++++-- compiler/sram/sram_base.py | 10 +++++----- compiler/verify/magic.py | 2 +- 3 files changed, 12 insertions(+), 8 deletions(-) diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index 21355b0e..f5a57324 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -180,8 +180,12 @@ class delay(simulation): self.dout_volt_meas.append(voltage_at_measure("v_{}".format(meas.name), meas.targ_name_no_port)) self.dout_volt_meas[-1].meta_str = meas.meta_str - - self.sen_meas = delay_measure("delay_sen", self.clk_frmt, self.sen_name+"{}", "FALL", "RISE", measure_scale=1e9) + + if not OPTS.use_pex: + self.sen_meas = delay_measure("delay_sen", self.clk_frmt, self.sen_name+"{}", "FALL", "RISE", measure_scale=1e9) + else: + self.sen_meas = delay_measure("delay_sen", self.clk_frmt, self.sen_name, "FALL", "RISE", measure_scale=1e9) + self.sen_meas.meta_str = sram_op.READ_ZERO self.sen_meas.meta_add_delay = True self.dout_volt_meas.append(self.sen_meas) diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index 6dc98835..ffaca694 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -111,16 +111,16 @@ class sram_base(design, verilog, lef): bl = [] br = [] - storage_layer_name = "metal1" - bitline_layer_name = "metal2" + storage_layer_name = "m1" + bitline_layer_name = "m2" for cell in range(len(bank_offset)): Q = [bank_offset[cell][0] + Q_offset[cell][0], bank_offset[cell][1] + Q_offset[cell][1]] Q_bar = [bank_offset[cell][0] + Q_bar_offset[cell][0], bank_offset[cell][1] + Q_bar_offset[cell][1]] OPTS.words_per_row = self.words_per_row - self.add_layout_pin_rect_center("bitcell_Q_b{0}_r{1}_c{2}".format(bank_num, int(cell % (OPTS.num_words / self.words_per_row)), int(cell / (OPTS.word_size * self.words_per_row))) , storage_layer_name, Q) - self.add_layout_pin_rect_center("bitcell_Q_bar_b{0}_r{1}_c{2}".format(bank_num, int(cell % (OPTS.num_words / self.words_per_row)), int(cell / (OPTS.word_size * self.words_per_row))), storage_layer_name, Q_bar) - + self.add_layout_pin_rect_center("bitcell_Q_b{}_r{}_c{}".format(bank_num, int(cell % (OPTS.num_words / self.words_per_row)), int(cell / (OPTS.num_words))) , storage_layer_name, Q) + self.add_layout_pin_rect_center("bitcell_Q_bar_b{}_r{}_c{}".format(bank_num, int(cell % (OPTS.num_words / self.words_per_row)), int(cell / (OPTS.num_words))), storage_layer_name, Q_bar) + for cell in range(len(bl_offsets)): col = bl_meta[cell][0][2] for bitline in range(len(bl_offsets[cell])): diff --git a/compiler/verify/magic.py b/compiler/verify/magic.py index 1be2f2cd..dcdf6951 100644 --- a/compiler/verify/magic.py +++ b/compiler/verify/magic.py @@ -464,7 +464,7 @@ def correct_port(name, output_file_name, ref_file_name): control_list = "+ " for bank in range(OPTS.num_banks): - control_list += "s_en{0}".format(bank) + control_list += "bank_{}/s_en0".format(bank) control_list += '\n' part2 = bitcell_list + control_list + part2 From 38648027d0e4cc4cabb45877aaf36e3f3ccc289d Mon Sep 17 00:00:00 2001 From: jcirimel Date: Tue, 4 Aug 2020 04:40:20 -0700 Subject: [PATCH 23/31] fix pinv unit test --- compiler/verify/magic.py | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/compiler/verify/magic.py b/compiler/verify/magic.py index dcdf6951..25d36a5e 100644 --- a/compiler/verify/magic.py +++ b/compiler/verify/magic.py @@ -450,21 +450,22 @@ def correct_port(name, output_file_name, ref_file_name): part2 = pex_file.read() bitcell_list = "+ " - for bank in range(OPTS.num_banks): + if OPTS.words_per_row: for bank in range(OPTS.num_banks): - row = int(OPTS.num_words / OPTS.words_per_row) - 1 - col = int(OPTS.word_size * OPTS.words_per_row) - 1 - bitcell_list += "bitcell_Q_b{0}_r{1}_c{2} ".format(bank,row,col) - bitcell_list += "bitcell_Q_bar_b{0}_r{1}_c{2} ".format(bank,row,col) - for col in range(OPTS.word_size * OPTS.words_per_row): - for port in range(OPTS.num_r_ports + OPTS.num_w_ports + OPTS.num_rw_ports): - bitcell_list += "bl{0}_{1} ".format(bank, col) - bitcell_list += "br{0}_{1} ".format(bank, col) + for bank in range(OPTS.num_banks): + row = int(OPTS.num_words / OPTS.words_per_row) - 1 + col = int(OPTS.word_size * OPTS.words_per_row) - 1 + bitcell_list += "bitcell_Q_b{0}_r{1}_c{2} ".format(bank,row,col) + bitcell_list += "bitcell_Q_bar_b{0}_r{1}_c{2} ".format(bank,row,col) + for col in range(OPTS.word_size * OPTS.words_per_row): + for port in range(OPTS.num_r_ports + OPTS.num_w_ports + OPTS.num_rw_ports): + bitcell_list += "bl{0}_{1} ".format(bank, col) + bitcell_list += "br{0}_{1} ".format(bank, col) bitcell_list += "\n" - control_list = "+ " - for bank in range(OPTS.num_banks): - control_list += "bank_{}/s_en0".format(bank) + if OPTS.words_per_row: + for bank in range(OPTS.num_banks): + control_list += "bank_{}/s_en0".format(bank) control_list += '\n' part2 = bitcell_list + control_list + part2 @@ -490,4 +491,4 @@ def print_drc_stats(): def print_lvs_stats(): debug.info(1,"LVS runs: {0}".format(num_lvs_runs)) def print_pex_stats(): - debug.info(1,"PEX runs: {0}".format(num_pex_runs)) \ No newline at end of file + debug.info(1,"PEX runs: {0}".format(num_pex_runs)) From 19f4e30989f3291ba8150617db7a55bf643a14ec Mon Sep 17 00:00:00 2001 From: jcirimel Date: Tue, 4 Aug 2020 15:21:54 -0700 Subject: [PATCH 24/31] change Qbar to Q_bar in freepdk45 bitcells --- technology/freepdk45/sp_lib/cell_6t.sp | 6 +++--- technology/freepdk45/sp_lib/dummy_cell_6t.sp | 10 +++++----- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/technology/freepdk45/sp_lib/cell_6t.sp b/technology/freepdk45/sp_lib/cell_6t.sp index e1e4936d..3a66fc9a 100644 --- a/technology/freepdk45/sp_lib/cell_6t.sp +++ b/technology/freepdk45/sp_lib/cell_6t.sp @@ -5,11 +5,11 @@ MM0 Qbar Q gnd gnd NMOS_VTG W=205.00n L=50n MM4 Qbar Q vdd vdd PMOS_VTG W=90n L=50n * Inverer 2 -MM1 Q Qbar gnd gnd NMOS_VTG W=205.00n L=50n -MM5 Q Qbar vdd vdd PMOS_VTG W=90n L=50n +MM1 Q Q_bar gnd gnd NMOS_VTG W=205.00n L=50n +MM5 Q Q_bar vdd vdd PMOS_VTG W=90n L=50n * Access transistors MM3 bl wl Q gnd NMOS_VTG W=135.00n L=50n -MM2 br wl Qbar gnd NMOS_VTG W=135.00n L=50n +MM2 br wl Q_bar gnd NMOS_VTG W=135.00n L=50n .ENDS cell_6t diff --git a/technology/freepdk45/sp_lib/dummy_cell_6t.sp b/technology/freepdk45/sp_lib/dummy_cell_6t.sp index ab862ec5..6e192049 100644 --- a/technology/freepdk45/sp_lib/dummy_cell_6t.sp +++ b/technology/freepdk45/sp_lib/dummy_cell_6t.sp @@ -1,15 +1,15 @@ .SUBCKT dummy_cell_6t bl br wl vdd gnd * Inverter 1 -MM0 Qbar Q gnd gnd NMOS_VTG W=205.00n L=50n -MM4 Qbar Q vdd vdd PMOS_VTG W=90n L=50n +MM0 Q_bar Q gnd gnd NMOS_VTG W=205.00n L=50n +MM4 Q_bar Q vdd vdd PMOS_VTG W=90n L=50n * Inverer 2 -MM1 Q Qbar gnd gnd NMOS_VTG W=205.00n L=50n -MM5 Q Qbar vdd vdd PMOS_VTG W=90n L=50n +MM1 Q Q_bar gnd gnd NMOS_VTG W=205.00n L=50n +MM5 Q Q_bar vdd vdd PMOS_VTG W=90n L=50n * Access transistors MM3 bl_noconn wl Q gnd NMOS_VTG W=135.00n L=50n -MM2 br_noconn wl Qbar gnd NMOS_VTG W=135.00n L=50n +MM2 br_noconn wl Q_bar gnd NMOS_VTG W=135.00n L=50n .ENDS cell_6t From 35eac54c0d7c3f93944808da62ff624771387417 Mon Sep 17 00:00:00 2001 From: jcirimel Date: Mon, 17 Aug 2020 17:47:43 -0700 Subject: [PATCH 25/31] update freepdk bitcell for pex --- technology/freepdk45/sp_lib/cell_6t.sp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/technology/freepdk45/sp_lib/cell_6t.sp b/technology/freepdk45/sp_lib/cell_6t.sp index 3a66fc9a..b39427d7 100644 --- a/technology/freepdk45/sp_lib/cell_6t.sp +++ b/technology/freepdk45/sp_lib/cell_6t.sp @@ -1,8 +1,8 @@ .SUBCKT cell_6t bl br wl vdd gnd * Inverter 1 -MM0 Qbar Q gnd gnd NMOS_VTG W=205.00n L=50n -MM4 Qbar Q vdd vdd PMOS_VTG W=90n L=50n +MM0 Q_bar Q gnd gnd NMOS_VTG W=205.00n L=50n +MM4 Q_bar Q vdd vdd PMOS_VTG W=90n L=50n * Inverer 2 MM1 Q Q_bar gnd gnd NMOS_VTG W=205.00n L=50n From 42f2ff679e6422272d18fc7f012136a82480ce03 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Thu, 27 Aug 2020 15:40:41 -0700 Subject: [PATCH 26/31] Removed dead code from delay and base module related to characterization --- compiler/base/hierarchy_design.py | 10 ---------- compiler/characterizer/delay.py | 30 ------------------------------ 2 files changed, 40 deletions(-) diff --git a/compiler/base/hierarchy_design.py b/compiler/base/hierarchy_design.py index 79b5a53a..ea6a3f44 100644 --- a/compiler/base/hierarchy_design.py +++ b/compiler/base/hierarchy_design.py @@ -222,16 +222,6 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): return self == mod and \ child_net.lower() == alias_net.lower() and \ parent_net.lower() == alias_net.lower() - - def get_mod_net(self, parent_net, child_inst, child_conns): - """ - Given an instance and net, returns the internal net in the mod - corresponding to input net. - """ - for conn, pin in zip(child_conns, child_inst.mod.pins): - if parent_net.lower() == conn.lower(): - return pin - return None def translate_nets(self, subinst_ports, port_dict, inst_name): """Converts connection names to their spice hierarchy equivalent""" diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index da1b8147..556e02bb 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -366,36 +366,6 @@ class delay(simulation): # so it makes the search awkward return set(factory.get_mods(OPTS.replica_bitline)) - def get_primary_cell_mod(self, cell_mods): - """ - Distinguish bitcell array mod from replica bitline array. - Assume there are no replica bitcells in the primary array. - """ - if len(cell_mods) == 1: - return cell_mods[0] - rbc_mods = factory.get_mods(OPTS.replica_bitcell) - non_rbc_mods = [] - for bitcell in cell_mods: - has_cell = False - for replica_cell in rbc_mods: - has_cell = has_cell or replica_cell.contains(bitcell, replica_cell.mods) - if not has_cell: - non_rbc_mods.append(bitcell) - if len(non_rbc_mods) != 1: - debug.error('Multiple bitcell mods found. Cannot distinguish for characterization',1) - return non_rbc_mods[0] - - def are_mod_pins_equal(self, mods): - """Determines if there are pins differences in the input mods""" - - if len(mods) == 0: - return True - pins = mods[0].pins - for mod in mods[1:]: - if pins != mod.pins: - return False - return True - def get_alias_in_path(self, paths, int_net, mod, exclusion_set=None): """ Finds a single alias for the int_net in given paths. From 73b2277daa38b35e1469cfdf19f00487f7cb58c7 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Thu, 27 Aug 2020 17:30:58 -0700 Subject: [PATCH 27/31] Removed dead code related to older characterization scheme --- compiler/custom/dff.py | 6 - compiler/modules/bank.py | 36 --- compiler/modules/bitcell_array.py | 7 - compiler/modules/control_logic.py | 226 ------------------ compiler/modules/delay_chain.py | 22 -- compiler/modules/dff_array.py | 6 - compiler/modules/dff_buf.py | 7 - compiler/modules/dff_buf_array.py | 6 - compiler/modules/dff_inv.py | 4 - compiler/modules/dff_inv_array.py | 8 +- compiler/modules/dummy_array.py | 9 +- compiler/modules/hierarchical_decoder.py | 8 - compiler/modules/precharge_array.py | 10 - compiler/modules/replica_bitcell_array.py | 7 - compiler/modules/sense_amp.py | 7 - compiler/modules/sense_amp_array.py | 15 -- .../modules/single_level_column_mux_array.py | 7 - compiler/modules/wordline_driver_array.py | 21 -- compiler/modules/write_driver_array.py | 4 - compiler/modules/write_mask_and_array.py | 5 - compiler/pgates/pand2.py | 19 +- compiler/pgates/pand3.py | 19 +- compiler/pgates/pbuf.py | 19 +- compiler/pgates/pdriver.py | 22 +- compiler/pgates/pinvbuf.py | 33 --- compiler/pgates/precharge.py | 9 +- compiler/pgates/single_level_column_mux.py | 15 -- compiler/sram/sram_1bank.py | 14 -- compiler/sram/sram_base.py | 48 +--- 29 files changed, 9 insertions(+), 610 deletions(-) diff --git a/compiler/custom/dff.py b/compiler/custom/dff.py index c8fdb4b0..cb703707 100644 --- a/compiler/custom/dff.py +++ b/compiler/custom/dff.py @@ -55,12 +55,6 @@ class dff(design.design): transition_prob = 0.5 return transition_prob*(c_load + c_para) - def get_clk_cin(self): - """Return the total capacitance (in relative units) that the clock is loaded by in the dff""" - #This is a handmade cell so the value must be entered in the tech.py file or estimated. - #Calculated in the tech file by summing the widths of all the gates and dividing by the minimum width. - return parameter["dff_clk_cin"] - def build_graph(self, graph, inst_name, port_nets): """Adds edges based on inputs/outputs. Overrides base class function.""" self.add_graph_edges(graph, port_nets) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 12a3b037..45900370 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -1039,42 +1039,6 @@ class bank(design.design): self.add_via_center(layers=self.m1_stack, offset=control_pos) - def determine_wordline_stage_efforts(self, external_cout, inp_is_rise=True): - """Get the all the stage efforts for each stage in the path within the bank clk_buf to a wordline""" - # Decoder is assumed to have settled before the negative edge of the clock. - # Delay model relies on this assumption - stage_effort_list = [] - wordline_cout = self.bitcell_array.get_wordline_cin() + external_cout - stage_effort_list += self.port_address.wordline_driver.determine_wordline_stage_efforts(wordline_cout, - inp_is_rise) - - return stage_effort_list - - def get_wl_en_cin(self): - """Get the relative capacitance of all the clk connections in the bank""" - # wl_en only used in the wordline driver. - return self.port_address.wordline_driver.get_wl_en_cin() - - def get_w_en_cin(self): - """Get the relative capacitance of all the clk connections in the bank""" - # wl_en only used in the wordline driver. - port = self.write_ports[0] - return self.port_data[port].write_driver.get_w_en_cin() - - def get_clk_bar_cin(self): - """Get the relative capacitance of all the clk_bar connections in the bank""" - # Current bank only uses clock bar (clk_buf_bar) as an enable for the precharge array. - - # Precharges are the all the same in Mulitport, one is picked - port = self.read_ports[0] - return self.port_data[port].precharge_array.get_en_cin() - - def get_sen_cin(self): - """Get the relative capacitance of all the sense amp enable connections in the bank""" - # Current bank only uses sen as an enable for the sense amps. - port = self.read_ports[0] - return self.port_data[port].sense_amp_array.get_en_cin() - def graph_exclude_precharge(self): """Precharge adds a loop between bitlines, can be excluded to reduce complexity""" for port in self.read_ports: diff --git a/compiler/modules/bitcell_array.py b/compiler/modules/bitcell_array.py index 81f1062f..24af458d 100644 --- a/compiler/modules/bitcell_array.py +++ b/compiler/modules/bitcell_array.py @@ -97,13 +97,6 @@ class bitcell_array(bitcell_base_array): bl_wire.wire_c =spice["min_tx_drain_c"] + bl_wire.wire_c return bl_wire - def get_wordline_cin(self): - """Get the relative input capacitance from the wordline connections in all the bitcell""" - # A single wordline is connected to all the bitcells in a single row meaning the capacitance depends on the # of columns - bitcell_wl_cin = self.cell.get_wl_cin() - total_cin = bitcell_wl_cin * self.column_size - return total_cin - def graph_exclude_bits(self, targ_row, targ_col): """Excludes bits in column from being added to graph except target""" # Function is not robust with column mux configurations diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index 706888de..e99d7b89 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -156,96 +156,12 @@ class control_logic(design.design): self.nand2 = factory.create(module_type="pnand2", height=dff_height) self.add_mod(self.nand2) - - # if (self.port_type == "rw") or (self.port_type == "r"): - # from importlib import reload - # self.delay_chain_resized = False - # c = reload(__import__(OPTS.replica_bitline)) - # replica_bitline = getattr(c, OPTS.replica_bitline) - # bitcell_loads = int(math.ceil(self.num_rows * OPTS.rbl_delay_percentage)) - # #Use a model to determine the delays with that heuristic - # if OPTS.use_tech_delay_chain_size: #Use tech parameters if set. - # fanout_list = OPTS.delay_chain_stages*[OPTS.delay_chain_fanout_per_stage] - # debug.info(1, "Using tech parameters to size delay chain: fanout_list={}".format(fanout_list)) - # self.replica_bitline = factory.create(module_type="replica_bitline", - # delay_fanout_list=fanout_list, - # bitcell_loads=bitcell_loads) - # if self.sram != None: #Calculate model value even for specified sizes - # self.set_sen_wl_delays() - - # else: #Otherwise, use a heuristic and/or model based sizing. - # #First use a heuristic - # delay_stages_heuristic, delay_fanout_heuristic = self.get_heuristic_delay_chain_size() - # self.replica_bitline = factory.create(module_type="replica_bitline", - # delay_fanout_list=[delay_fanout_heuristic]*delay_stages_heuristic, - # bitcell_loads=bitcell_loads) - # #Resize if necessary, condition depends on resizing method - # if self.sram != None and self.enable_delay_chain_resizing and not self.does_sen_rise_fall_timing_match(): - # #This resizes to match fall and rise delays, can make the delay chain weird sizes. - # stage_list = self.get_dynamic_delay_fanout_list(delay_stages_heuristic, delay_fanout_heuristic) - # self.replica_bitline = factory.create(module_type="replica_bitline", - # delay_fanout_list=stage_list, - # bitcell_loads=bitcell_loads) - - # #This resizes based on total delay. - # # delay_stages, delay_fanout = self.get_dynamic_delay_chain_size(delay_stages_heuristic, delay_fanout_heuristic) - # # self.replica_bitline = factory.create(module_type="replica_bitline", - # # delay_fanout_list=[delay_fanout]*delay_stages, - # # bitcell_loads=bitcell_loads) - - # self.sen_delay_rise,self.sen_delay_fall = self.get_delays_to_sen() #get the new timing - # self.delay_chain_resized = True debug.check(OPTS.delay_chain_stages % 2, "Must use odd number of delay chain stages for inverting delay chain.") self.delay_chain=factory.create(module_type="delay_chain", fanout_list = OPTS.delay_chain_stages * [ OPTS.delay_chain_fanout_per_stage ]) self.add_mod(self.delay_chain) - - def get_heuristic_delay_chain_size(self): - """Use a basic heuristic to determine the size of the delay chain used for the Sense Amp Enable """ - # FIXME: The minimum was 2 fanout, now it will not pass DRC unless it is 3. Why? - delay_fanout = 3 # This can be anything >=3 - # Model poorly captures delay of the column mux. Be pessismistic for column mux - if self.words_per_row >= 2: - delay_stages = 8 - else: - delay_stages = 2 - - # Read ports have a shorter s_en delay. The model is not accurate enough to catch this difference - # on certain sram configs. - if self.port_type == "r": - delay_stages+=2 - - return (delay_stages, delay_fanout) - - def set_sen_wl_delays(self): - """Set delays for wordline and sense amp enable""" - self.wl_delay_rise, self.wl_delay_fall = self.get_delays_to_wl() - self.sen_delay_rise, self.sen_delay_fall = self.get_delays_to_sen() - self.wl_delay = self.wl_delay_rise + self.wl_delay_fall - self.sen_delay = self.sen_delay_rise + self.sen_delay_fall - - def does_sen_rise_fall_timing_match(self): - """Compare the relative rise/fall delays of the sense amp enable and wordline""" - self.set_sen_wl_delays() - # This is not necessarily more reliable than total delay in some cases. - if (self.wl_delay_rise * self.wl_timing_tolerance >= self.sen_delay_rise or - self.wl_delay_fall * self.wl_timing_tolerance >= self.sen_delay_fall): - return False - else: - return True - - def does_sen_total_timing_match(self): - """Compare the total delays of the sense amp enable and wordline""" - self.set_sen_wl_delays() - # The sen delay must always be bigger than than the wl - # delay. This decides how much larger the sen delay must be - # before a re-size is warranted. - if self.wl_delay * self.wl_timing_tolerance >= self.sen_delay: - return False - else: - return True def get_dynamic_delay_chain_size(self, previous_stages, previous_fanout): """Determine the size of the delay chain used for the Sense Amp Enable using path delays""" @@ -333,17 +249,6 @@ class control_logic(design.design): delay_per_stage = fanout + 1 + self.inv_parasitic_delay delay_stages = ceil(required_delay / delay_per_stage) return delay_stages - - def calculate_stage_list(self, total_stages, fanout_rise, fanout_fall): - """ - Produces a list of fanouts which determine the size of the delay chain. - List length is the number of stages. - Assumes the first stage is falling. - """ - stage_list = [] - for i in range(total_stages): - if i % 2 == 0: - stage_list.append() def setup_signal_busses(self): """ Setup bus names, determine the size of the busses etc """ @@ -869,137 +774,6 @@ class control_logic(design.design): offset=pin.ll(), height=pin.height(), width=pin.width()) - def get_delays_to_wl(self): - """Get the delay (in delay units) of the clk to a wordline in the bitcell array""" - debug.check(self.sram.all_mods_except_control_done, "Cannot calculate sense amp enable delay unless all module have been added.") - self.wl_stage_efforts = self.get_wordline_stage_efforts() - clk_to_wl_rise, clk_to_wl_fall = logical_effort.calculate_relative_rise_fall_delays(self.wl_stage_efforts) - total_delay = clk_to_wl_rise + clk_to_wl_fall - debug.info(1, - "Clock to wl delay is rise={:.3f}, fall={:.3f}, total={:.3f} in delay units".format(clk_to_wl_rise, - clk_to_wl_fall, - total_delay)) - return clk_to_wl_rise, clk_to_wl_fall - - def get_wordline_stage_efforts(self): - """Follows the gated_clk_bar -> wl_en -> wordline signal for the total path efforts""" - stage_effort_list = [] - - # Initial direction of gated_clk_bar signal for this path - is_clk_bar_rise = True - - # Calculate the load on wl_en within the module and add it to external load - external_cout = self.sram.get_wl_en_cin() - # First stage is the clock buffer - stage_effort_list += self.clk_buf_driver.get_stage_efforts(external_cout, is_clk_bar_rise) - last_stage_is_rise = stage_effort_list[-1].is_rise - - # Then ask the sram for the other path delays (from the bank) - stage_effort_list += self.sram.get_wordline_stage_efforts(last_stage_is_rise) - - return stage_effort_list - - def get_delays_to_sen(self): - """ - Get the delay (in delay units) of the clk to a sense amp enable. - This does not incorporate the delay of the replica bitline. - """ - debug.check(self.sram.all_mods_except_control_done, "Cannot calculate sense amp enable delay unless all module have been added.") - self.sen_stage_efforts = self.get_sa_enable_stage_efforts() - clk_to_sen_rise, clk_to_sen_fall = logical_effort.calculate_relative_rise_fall_delays(self.sen_stage_efforts) - total_delay = clk_to_sen_rise + clk_to_sen_fall - debug.info(1, - "Clock to s_en delay is rise={:.3f}, fall={:.3f}, total={:.3f} in delay units".format(clk_to_sen_rise, - clk_to_sen_fall, - total_delay)) - return clk_to_sen_rise, clk_to_sen_fall - - def get_sa_enable_stage_efforts(self): - """Follows the gated_clk_bar signal to the sense amp enable signal adding each stages stage effort to a list""" - stage_effort_list = [] - - # Initial direction of clock signal for this path - last_stage_rise = True - - # First stage, gated_clk_bar -(and2)-> rbl_in. Only for RW ports. - if self.port_type == "rw": - stage1_cout = self.replica_bitline.get_en_cin() - stage_effort_list += self.and2.get_stage_efforts(stage1_cout, last_stage_rise) - last_stage_rise = stage_effort_list[-1].is_rise - - # Replica bitline stage, rbl_in -(rbl)-> pre_s_en - stage2_cout = self.sen_and2.get_cin() - stage_effort_list += self.replica_bitline.determine_sen_stage_efforts(stage2_cout, last_stage_rise) - last_stage_rise = stage_effort_list[-1].is_rise - - # buffer stage, pre_s_en -(buffer)-> s_en - stage3_cout = self.sram.get_sen_cin() - stage_effort_list += self.s_en_driver.get_stage_efforts(stage3_cout, last_stage_rise) - last_stage_rise = stage_effort_list[-1].is_rise - - return stage_effort_list - - def get_wl_sen_delays(self): - """ Gets a list of the stages and delays in order of their path. """ - - if self.sen_stage_efforts == None or self.wl_stage_efforts == None: - debug.error("Model delays not calculated for SRAM.", 1) - wl_delays = logical_effort.calculate_delays(self.wl_stage_efforts) - sen_delays = logical_effort.calculate_delays(self.sen_stage_efforts) - return wl_delays, sen_delays - - def analytical_delay(self, corner, slew, load): - """ Gets the analytical delay from clk input to wl_en output """ - - stage_effort_list = [] - # Calculate the load on clk_buf_bar - # ext_clk_buf_cout = self.sram.get_clk_bar_cin() - - # Operations logic starts on negative edge - last_stage_rise = False - - # First stage(s), clk -(pdriver)-> clk_buf. - # clk_buf_cout = self.replica_bitline.get_en_cin() - clk_buf_cout = 0 - stage_effort_list += self.clk_buf_driver.get_stage_efforts(clk_buf_cout, last_stage_rise) - last_stage_rise = stage_effort_list[-1].is_rise - - # Second stage, clk_buf -(inv)-> clk_bar - clk_bar_cout = self.and2.get_cin() - stage_effort_list += self.and2.get_stage_efforts(clk_bar_cout, last_stage_rise) - last_stage_rise = stage_effort_list[-1].is_rise - - # Third stage clk_bar -(and)-> gated_clk_bar - gated_clk_bar_cin = self.get_gated_clk_bar_cin() - stage_effort_list.append(self.inv.get_stage_effort(gated_clk_bar_cin, last_stage_rise)) - last_stage_rise = stage_effort_list[-1].is_rise - - # Stages from gated_clk_bar -------> wordline - stage_effort_list += self.get_wordline_stage_efforts() - return stage_effort_list - - def get_clk_buf_cin(self): - """ - Get the loads that are connected to the buffered clock. - Includes all the DFFs and some logic. - """ - - # Control logic internal load - int_clk_buf_cap = self.inv.get_cin() + self.ctrl_dff_array.get_clk_cin() + self.and2.get_cin() - - # Control logic external load (in the other parts of the SRAM) - ext_clk_buf_cap = self.sram.get_clk_bar_cin() - - return int_clk_buf_cap + ext_clk_buf_cap - - def get_gated_clk_bar_cin(self): - """Get intermediates net gated_clk_bar's capacitance""" - - total_cin = 0 - total_cin += self.wl_en_driver.get_cin() - if self.port_type == 'rw': - total_cin += self.and2.get_cin() - return total_cin def graph_exclude_dffs(self): """Exclude dffs from graph as they do not represent critical path""" diff --git a/compiler/modules/delay_chain.py b/compiler/modules/delay_chain.py index 246299c1..30126b63 100644 --- a/compiler/modules/delay_chain.py +++ b/compiler/modules/delay_chain.py @@ -210,25 +210,3 @@ class delay_chain(design.design): layer="m2", start=mid_point, end=mid_point.scale(1, 0)) - - def get_cin(self): - """Get the enable input ralative capacitance""" - # Only 1 input to the delay chain which is connected to an inverter. - dc_cin = self.inv.get_cin() - return dc_cin - - def determine_delayed_en_stage_efforts(self, ext_delayed_en_cout, inp_is_rise=True): - """Get the stage efforts from the en to s_en. Does not compute the delay for the bitline load.""" - stage_effort_list = [] - # Add a stage to the list for every stage in delay chain. - # Stages only differ in fanout except the last which has an external cout. - last_stage_is_rise = inp_is_rise - for stage_fanout in self.fanout_list: - stage_cout = self.inv.get_cin() * (stage_fanout + 1) - if len(stage_effort_list) == len(self.fanout_list) - 1: - stage_cout+=ext_delayed_en_cout - stage = self.inv.get_stage_effort(stage_cout, last_stage_is_rise) - stage_effort_list.append(stage) - last_stage_is_rise = stage.is_rise - - return stage_effort_list diff --git a/compiler/modules/dff_array.py b/compiler/modules/dff_array.py index c4f85a6d..cb82443b 100644 --- a/compiler/modules/dff_array.py +++ b/compiler/modules/dff_array.py @@ -155,9 +155,3 @@ class dff_array(design.design): self.add_via_stack_center(from_layer=clk_pin.layer, to_layer="m3", offset=vector(clk_pin.cx(), clk_ypos)) - - def get_clk_cin(self): - """Return the total capacitance (in relative units) that the clock is loaded by in the dff array""" - dff_clk_cin = self.dff.get_clk_cin() - total_cin = dff_clk_cin * self.rows * self.columns - return total_cin diff --git a/compiler/modules/dff_buf.py b/compiler/modules/dff_buf.py index 1657d7a8..1290bf12 100644 --- a/compiler/modules/dff_buf.py +++ b/compiler/modules/dff_buf.py @@ -196,10 +196,3 @@ class dff_buf(design.design): self.add_via_stack_center(from_layer=a2_pin.layer, to_layer="m2", offset=qb_pos) - - def get_clk_cin(self): - """Return the total capacitance (in relative units) that the clock is loaded by in the dff""" - # This is a handmade cell so the value must be entered in the tech.py file or estimated. - # Calculated in the tech file by summing the widths of all the gates and dividing by the minimum width. - # FIXME: Dff changed in a past commit. The parameter need to be updated. - return parameter["dff_clk_cin"] diff --git a/compiler/modules/dff_buf_array.py b/compiler/modules/dff_buf_array.py index 88852d45..d6382973 100644 --- a/compiler/modules/dff_buf_array.py +++ b/compiler/modules/dff_buf_array.py @@ -227,9 +227,3 @@ class dff_buf_array(design.design): # Drop a via to the M3 pin self.add_via_center(layers=self.m2_stack, offset=vector(clk_pin.cx(), clk_ypos)) - - def get_clk_cin(self): - """Return the total capacitance (in relative units) that the clock is loaded by in the dff array""" - dff_clk_cin = self.dff.get_clk_cin() - total_cin = dff_clk_cin * self.rows * self.columns - return total_cin diff --git a/compiler/modules/dff_inv.py b/compiler/modules/dff_inv.py index 033312ef..8f50f9e8 100644 --- a/compiler/modules/dff_inv.py +++ b/compiler/modules/dff_inv.py @@ -150,7 +150,3 @@ class dff_inv(design.design): offset=dout_pin.center()) self.add_via_center(layers=self.m1_stack, offset=dout_pin.center()) - - def get_clk_cin(self): - """Return the total capacitance (in relative units) that the clock is loaded by in the dff""" - return self.dff.get_clk_cin() diff --git a/compiler/modules/dff_inv_array.py b/compiler/modules/dff_inv_array.py index 6b08bcce..1687e043 100644 --- a/compiler/modules/dff_inv_array.py +++ b/compiler/modules/dff_inv_array.py @@ -188,10 +188,4 @@ class dff_inv_array(design.design): height=self.height) # Drop a via to the M3 pin self.add_via_center(layers=self.m2_stack, - offset=vector(clk_pin.cx(),clk_ypos)) - - def get_clk_cin(self): - """Return the total capacitance (in relative units) that the clock is loaded by in the dff array""" - dff_clk_cin = self.dff.get_clk_cin() - total_cin = dff_clk_cin * self.rows * self.columns - return total_cin + offset=vector(clk_pin.cx(),clk_ypos)) diff --git a/compiler/modules/dummy_array.py b/compiler/modules/dummy_array.py index 9004994b..01446d85 100644 --- a/compiler/modules/dummy_array.py +++ b/compiler/modules/dummy_array.py @@ -54,12 +54,7 @@ class dummy_array(bitcell_base_array): self.connect_inst(self.get_bitcell_pins(row, col)) def input_load(self): + # FIXME: This appears to be old code from previous characterization. Needs to be updated. wl_wire = self.gen_wl_wire() return wl_wire.return_input_cap() - - def get_wordline_cin(self): - """Get the relative input capacitance from the wordline connections in all the bitcell""" - # A single wordline is connected to all the bitcells in a single row meaning the capacitance depends on the # of columns - bitcell_wl_cin = self.cell.get_wl_cin() - total_cin = bitcell_wl_cin * self.column_size - return total_cin + \ No newline at end of file diff --git a/compiler/modules/hierarchical_decoder.py b/compiler/modules/hierarchical_decoder.py index e32fe1c6..ca26993f 100644 --- a/compiler/modules/hierarchical_decoder.py +++ b/compiler/modules/hierarchical_decoder.py @@ -606,11 +606,3 @@ class hierarchical_decoder(design.design): to_layer=self.output_layer, offset=rail_pos, directions=self.bus_directions) - - def input_load(self): - if self.determine_predecodes(self.num_inputs)[1]==0: - pre = self.pre2_4 - else: - pre = self.pre3_8 - return pre.input_load() - diff --git a/compiler/modules/precharge_array.py b/compiler/modules/precharge_array.py index c2d3d986..00fe9885 100644 --- a/compiler/modules/precharge_array.py +++ b/compiler/modules/precharge_array.py @@ -125,13 +125,3 @@ class precharge_array(design.design): offset = vector(tempx, 0) self.local_insts[i].place(offset=offset, mirror=mirror) xoffset = xoffset + self.pc_cell.width - - def get_en_cin(self): - """ - Get the relative capacitance of all the clk connections - in the precharge array - """ - # Assume single port - precharge_en_cin = self.pc_cell.get_en_cin() - return precharge_en_cin * self.columns - diff --git a/compiler/modules/replica_bitcell_array.py b/compiler/modules/replica_bitcell_array.py index 14d7c858..64ae404e 100644 --- a/compiler/modules/replica_bitcell_array.py +++ b/compiler/modules/replica_bitcell_array.py @@ -552,13 +552,6 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array): bl_wire.wire_c =spice["min_tx_drain_c"] + bl_wire.wire_c # 1 access tx d/s per cell return bl_wire - def get_wordline_cin(self): - """Get the relative input capacitance from the wordline connections in all the bitcell""" - # A single wordline is connected to all the bitcells in a single row meaning the capacitance depends on the # of columns - bitcell_wl_cin = self.cell.get_wl_cin() - total_cin = bitcell_wl_cin * self.column_size - return total_cin - def graph_exclude_bits(self, targ_row, targ_col): """Excludes bits in column from being added to graph except target""" self.bitcell_array.graph_exclude_bits(targ_row, targ_col) diff --git a/compiler/modules/sense_amp.py b/compiler/modules/sense_amp.py index 67703903..f1d5de92 100644 --- a/compiler/modules/sense_amp.py +++ b/compiler/modules/sense_amp.py @@ -82,13 +82,6 @@ class sense_amp(design.design): # Power in this module currently not defined. Returns 0 nW (leakage and dynamic). total_power = self.return_power() return total_power - - def get_en_cin(self): - """Get the relative capacitance of sense amp enable gate cin""" - pmos_cin = parameter["sa_en_pmos_size"] / drc("minwidth_tx") - nmos_cin = parameter["sa_en_nmos_size"] / drc("minwidth_tx") - # sen is connected to 2 pmos isolation TX and 1 nmos per sense amp. - return 2 * pmos_cin + nmos_cin def get_enable_name(self): """Returns name used for enable net""" diff --git a/compiler/modules/sense_amp_array.py b/compiler/modules/sense_amp_array.py index 20f6e06f..6d0b85d2 100644 --- a/compiler/modules/sense_amp_array.py +++ b/compiler/modules/sense_amp_array.py @@ -190,18 +190,3 @@ class sense_amp_array(design.design): self.add_via_stack_center(from_layer=en_pin.layer, to_layer=self.en_layer, offset=inst.get_pin(self.amp.en_name).center()) - - def input_load(self): - return self.amp.input_load() - - def get_en_cin(self): - """Get the relative capacitance of all the sense amp enable connections in the array""" - sense_amp_en_cin = self.amp.get_en_cin() - return sense_amp_en_cin * self.word_size - - def get_drain_cin(self): - """Get the relative capacitance of the drain of the PMOS isolation TX""" - from tech import parameter - # Bitcell drain load being used to estimate PMOS drain load - drain_load = logical_effort.convert_farad_to_relative_c(parameter['bitcell_drain_cap']) - return drain_load diff --git a/compiler/modules/single_level_column_mux_array.py b/compiler/modules/single_level_column_mux_array.py index f57bbb20..267b2a6a 100644 --- a/compiler/modules/single_level_column_mux_array.py +++ b/compiler/modules/single_level_column_mux_array.py @@ -230,10 +230,3 @@ class single_level_column_mux_array(design.design): to_layer=self.sel_layer, offset=br_out_offset_begin, directions=self.via_directions) - - def get_drain_cin(self): - """Get the relative capacitance of the drain of the NMOS pass TX""" - from tech import parameter - # Bitcell drain load being used to estimate mux NMOS drain load - drain_load = logical_effort.convert_farad_to_relative_c(parameter['bitcell_drain_cap']) - return drain_load diff --git a/compiler/modules/wordline_driver_array.py b/compiler/modules/wordline_driver_array.py index f82938de..ac0a0cb2 100644 --- a/compiler/modules/wordline_driver_array.py +++ b/compiler/modules/wordline_driver_array.py @@ -159,24 +159,3 @@ class wordline_driver_array(design.design): layer=self.route_layer, start=wl_offset, end=wl_offset - vector(self.m1_width, 0)) - - def determine_wordline_stage_efforts(self, external_cout, inp_is_rise=True): - """ - Follows the clk_buf to a wordline signal adding - each stages stage effort to a list. - """ - stage_effort_list = [] - - stage1 = self.wl_driver.get_stage_effort(external_cout, inp_is_rise) - stage_effort_list.append(stage1) - - return stage_effort_list - - def get_wl_en_cin(self): - """ - Get the relative capacitance of all - the enable connections in the bank - """ - # The enable is connected to a and2 for every row. - total_cin = self.wl_driver.get_cin() * self.rows - return total_cin diff --git a/compiler/modules/write_driver_array.py b/compiler/modules/write_driver_array.py index 665142ec..b7bcd6b3 100644 --- a/compiler/modules/write_driver_array.py +++ b/compiler/modules/write_driver_array.py @@ -265,7 +265,3 @@ class write_driver_array(design.design): offset=inst.get_pin(inst.mod.en_name).ll().scale(0, 1), width=self.width) - def get_w_en_cin(self): - """Get the relative capacitance of all the enable connections in the bank""" - # The enable is connected to a nand2 for every row. - return self.driver.get_w_en_cin() * len(self.driver_insts) diff --git a/compiler/modules/write_mask_and_array.py b/compiler/modules/write_mask_and_array.py index 9b083512..04563209 100644 --- a/compiler/modules/write_mask_and_array.py +++ b/compiler/modules/write_mask_and_array.py @@ -140,8 +140,3 @@ class write_mask_and_array(design.design): supply_pin_left = self.and2_insts[0].get_pin(supply) supply_pin_right = self.and2_insts[self.num_wmasks - 1].get_pin(supply) self.add_path(supply_pin_left.layer, [supply_pin_left.lc(), supply_pin_right.rc()]) - - def get_cin(self): - """Get the relative capacitance of all the input connections in the bank""" - # The enable is connected to an and2 for every row. - return self.and2.get_cin() * len(self.and2_insts) diff --git a/compiler/pgates/pand2.py b/compiler/pgates/pand2.py index a46485d0..21241056 100644 --- a/compiler/pgates/pand2.py +++ b/compiler/pgates/pand2.py @@ -146,21 +146,4 @@ class pand2(pgate.pgate): offset=pin.center(), width=pin.width(), height=pin.height()) - - def get_stage_efforts(self, external_cout, inp_is_rise=False): - """Get the stage efforts of the A or B -> Z path""" - stage_effort_list = [] - stage1_cout = self.inv.get_cin() - stage1 = self.nand.get_stage_effort(stage1_cout, inp_is_rise) - stage_effort_list.append(stage1) - last_stage_is_rise = stage1.is_rise - - stage2 = self.inv.get_stage_effort(external_cout, last_stage_is_rise) - stage_effort_list.append(stage2) - - return stage_effort_list - - def get_cin(self): - """Return the relative input capacitance of a single input""" - return self.nand.get_cin() - + \ No newline at end of file diff --git a/compiler/pgates/pand3.py b/compiler/pgates/pand3.py index 72a57f74..63d1cd0f 100644 --- a/compiler/pgates/pand3.py +++ b/compiler/pgates/pand3.py @@ -161,21 +161,4 @@ class pand3(pgate.pgate): slew=nand_delay.slew, load=load) return nand_delay + inv_delay - - def get_stage_efforts(self, external_cout, inp_is_rise=False): - """Get the stage efforts of the A or B -> Z path""" - stage_effort_list = [] - stage1_cout = self.inv.get_cin() - stage1 = self.nand.get_stage_effort(stage1_cout, inp_is_rise) - stage_effort_list.append(stage1) - last_stage_is_rise = stage1.is_rise - - stage2 = self.inv.get_stage_effort(external_cout, last_stage_is_rise) - stage_effort_list.append(stage2) - - return stage_effort_list - - def get_cin(self): - """Return the relative input capacitance of a single input""" - return self.nand.get_cin() - + \ No newline at end of file diff --git a/compiler/pgates/pbuf.py b/compiler/pgates/pbuf.py index d82e2091..e504b89e 100644 --- a/compiler/pgates/pbuf.py +++ b/compiler/pgates/pbuf.py @@ -96,21 +96,4 @@ class pbuf(pgate.pgate): offset=a_pin.center(), width=a_pin.width(), height=a_pin.height()) - - def get_stage_efforts(self, external_cout, inp_is_rise=False): - """Get the stage efforts of the A -> Z path""" - stage_effort_list = [] - stage1_cout = self.inv2.get_cin() - stage1 = self.inv1.get_stage_effort(stage1_cout, inp_is_rise) - stage_effort_list.append(stage1) - last_stage_is_rise = stage1.is_rise - - stage2 = self.inv2.get_stage_effort(external_cout, last_stage_is_rise) - stage_effort_list.append(stage2) - - return stage_effort_list - - def get_cin(self): - """Returns the relative capacitance of the input""" - input_cin = self.inv1.get_cin() - return input_cin + \ No newline at end of file diff --git a/compiler/pgates/pdriver.py b/compiler/pgates/pdriver.py index 8916f0fa..e48f9f6c 100644 --- a/compiler/pgates/pdriver.py +++ b/compiler/pgates/pdriver.py @@ -168,24 +168,4 @@ class pdriver(pgate.pgate): def get_sizes(self): """ Return the relative sizes of the buffers """ return self.size_list - - def get_stage_efforts(self, external_cout, inp_is_rise=False): - """ Get the stage efforts of the A -> Z path """ - cout_list = [] - for prev_inv, inv in zip(self.inv_list, self.inv_list[1:]): - cout_list.append(inv.get_cin()) - - cout_list.append(external_cout) - - stage_effort_list = [] - last_inp_is_rise = inp_is_rise - for inv, cout in zip(self.inv_list, cout_list): - stage = inv.get_stage_effort(cout, last_inp_is_rise) - stage_effort_list.append(stage) - last_inp_is_rise = stage.is_rise - - return stage_effort_list - - def get_cin(self): - """ Returns the relative capacitance of the input """ - return self.inv_list[0].get_cin() + \ No newline at end of file diff --git a/compiler/pgates/pinvbuf.py b/compiler/pgates/pinvbuf.py index f746736c..497bd3df 100644 --- a/compiler/pgates/pinvbuf.py +++ b/compiler/pgates/pinvbuf.py @@ -184,36 +184,3 @@ class pinvbuf(pgate.pgate): self.add_layout_pin_rect_center(text="A", layer=a_pin.layer, offset=a_pin.center()) - - def determine_clk_buf_stage_efforts(self, external_cout, inp_is_rise=False): - """Get the stage efforts of the clk -> clk_buf path""" - stage_effort_list = [] - stage1_cout = self.inv1.get_cin() + self.inv2.get_cin() - stage1 = self.inv.get_stage_effort(stage1_cout, inp_is_rise) - stage_effort_list.append(stage1) - last_stage_is_rise = stage1.is_rise - - stage2 = self.inv2.get_stage_effort(external_cout, last_stage_is_rise) - stage_effort_list.append(stage2) - - return stage_effort_list - - def determine_clk_buf_bar_stage_efforts(self, external_cout, inp_is_rise=False): - """Get the stage efforts of the clk -> clk_buf path""" - - # After (almost) every stage, the direction of the signal inverts. - stage_effort_list = [] - stage1_cout = self.inv1.get_cin() + self.inv2.get_cin() - stage1 = self.inv.get_stage_effort(stage1_cout, inp_is_rise) - stage_effort_list.append(stage1) - last_stage_is_rise = stage_effort_list[-1].is_rise - - stage2_cout = self.inv2.get_cin() - stage2 = self.inv1.get_stage_effort(stage2_cout, last_stage_is_rise) - stage_effort_list.append(stage2) - last_stage_is_rise = stage_effort_list[-1].is_rise - - stage3 = self.inv2.get_stage_effort(external_cout, last_stage_is_rise) - stage_effort_list.append(stage3) - - return stage_effort_list diff --git a/compiler/pgates/precharge.py b/compiler/pgates/precharge.py index aefdbb86..4ae48167 100644 --- a/compiler/pgates/precharge.py +++ b/compiler/pgates/precharge.py @@ -300,11 +300,4 @@ class precharge(design.design): self.add_path(self.bitline_layer, [left_pos, right_pos], width=pmos_pin.height()) - - def get_en_cin(self): - """Get the relative capacitance of the enable in the precharge cell""" - # The enable connect to three pmos gates - # They all use the same size pmos. - pmos_cin = self.pmos.get_cin() - return 3 * pmos_cin - + \ No newline at end of file diff --git a/compiler/pgates/single_level_column_mux.py b/compiler/pgates/single_level_column_mux.py index cd9be887..4873e6fc 100644 --- a/compiler/pgates/single_level_column_mux.py +++ b/compiler/pgates/single_level_column_mux.py @@ -241,18 +241,3 @@ class single_level_column_mux(pgate.pgate): offset=vector(0, 0), width=self.bitcell.width, height=self.height) - - def get_stage_effort(self, corner, slew, load): - """ - Returns relative delay that the column mux. - Difficult to convert to LE model. - """ - parasitic_delay = 1 - # This is not CMOS, so using this may be incorrect. - cin = 2 * self.tx_size - return logical_effort.logical_effort("column_mux", - self.tx_size, - cin, - load, - parasitic_delay, - False) diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py index 3f254b73..c67f7233 100644 --- a/compiler/sram/sram_1bank.py +++ b/compiler/sram/sram_1bank.py @@ -626,20 +626,6 @@ class sram_1bank(sram_base): # Insts located in control logic, exclusion function called here for inst in self.control_logic_insts: inst.mod.graph_exclude_dffs() - - def get_sen_name(self, sram_name, port=0): - """Returns the s_en spice name.""" - # Naming scheme is hardcoded using this function, should be built into the - # graph in someway. - sen_name = "s_en{}".format(port) - control_conns = self.get_conns(self.control_logic_insts[port]) - # Sanity checks - if sen_name not in control_conns: - debug.error("Signal={} not contained in control logic connections={}".format(sen_name, - control_conns)) - if sen_name in self.pins: - debug.error("Internal signal={} contained in port list. Name defined by the parent.".format(sen_name)) - return "X{}.{}".format(sram_name, sen_name) def get_cell_name(self, inst_name, row, col): """Gets the spice name of the target bitcell.""" diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index ffaca694..c9eb4ea1 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -630,50 +630,4 @@ class sram_base(design, verilog, lef): def lvs_write(self, sp_name): self.sp_write(sp_name, lvs_netlist=True) - - def get_wordline_stage_efforts(self, inp_is_rise=True): - """Get the all the stage efforts for each stage in the path from clk_buf to a wordline""" - stage_effort_list = [] - - # Clk_buf originates from the control logic so only the bank is related to the wordline path - # No loading on the wordline other than in the bank. - external_wordline_cout = 0 - stage_effort_list += self.bank.determine_wordline_stage_efforts(external_wordline_cout, inp_is_rise) - - return stage_effort_list - - def get_wl_en_cin(self): - """Gets the capacitive load the of clock (clk_buf) for the sram""" - # Only the wordline drivers within the bank use this signal - return self.bank.get_wl_en_cin() - - def get_w_en_cin(self): - """Gets the capacitive load the of write enable (w_en) for the sram""" - # Only the write drivers within the bank use this signal - return self.bank.get_w_en_cin() - - def get_p_en_bar_cin(self): - """Gets the capacitive load the of precharge enable (p_en_bar) for the sram""" - # Only the precharges within the bank use this signal - return self.bank.get_p_en_bar_cin() - - def get_clk_bar_cin(self): - """Gets the capacitive load the of clock (clk_buf_bar) for the sram""" - # As clk_buf_bar is an output of the control logic. The cap for that module is not determined here. - # Only the precharge cells use this signal (other than the control logic) - return self.bank.get_clk_bar_cin() - - def get_sen_cin(self): - """Gets the capacitive load the of sense amp enable for the sram""" - # Only the sense_amps use this signal (other than the control logic) - return self.bank.get_sen_cin() - - def get_dff_clk_buf_cin(self): - """Get the relative capacitance of the clk_buf signal. - Does not get the control logic loading but everything else""" - total_cin = 0 - total_cin += self.row_addr_dff.get_clk_cin() - total_cin += self.data_dff.get_clk_cin() - if self.col_addr_size > 0: - total_cin += self.col_addr_dff.get_clk_cin() - return total_cin + \ No newline at end of file From 13b1d4613c41c771930fcde481978506039b32d5 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Mon, 31 Aug 2020 14:36:13 -0700 Subject: [PATCH 28/31] Moved spice naming checking code from design to the spice base module --- compiler/base/hierarchy_design.py | 46 ------------------------------- compiler/base/hierarchy_spice.py | 45 ++++++++++++++++++++++++++++++ 2 files changed, 45 insertions(+), 46 deletions(-) diff --git a/compiler/base/hierarchy_design.py b/compiler/base/hierarchy_design.py index ea6a3f44..16d2bb4e 100644 --- a/compiler/base/hierarchy_design.py +++ b/compiler/base/hierarchy_design.py @@ -177,52 +177,6 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): name_dict[si_port.lower()] = mod_info subinst.mod.build_names(name_dict, subinst_name, subinst_ports) - def find_aliases(self, inst_name, port_nets, path_nets, alias, alias_mod, exclusion_set=None): - """Given a list of nets, will compare the internal alias of a mod to determine - if the nets have a connection to this mod's net (but not inst). - """ - if not exclusion_set: - exclusion_set = set() - try: - self.name_dict - except AttributeError: - self.name_dict = {} - self.build_names(self.name_dict, inst_name, port_nets) - aliases = [] - for net in path_nets: - net = net.lower() - int_net = self.name_dict[net]['int_net'] - int_mod = self.name_dict[net]['mod'] - if int_mod.is_net_alias(int_net, alias, alias_mod, exclusion_set): - aliases.append(net) - return aliases - - def is_net_alias(self, known_net, net_alias, mod, exclusion_set): - """Checks if the alias_net in input mod is the same as the input net for this mod (self).""" - if self in exclusion_set: - return False - # Check ports of this mod - for pin in self.pins: - if self.is_net_alias_name_check(known_net, pin, net_alias, mod): - return True - # Check connections of all other subinsts - mod_set = set() - for subinst, inst_conns in zip(self.insts, self.conns): - for inst_conn, mod_pin in zip(inst_conns, subinst.mod.pins): - if self.is_net_alias_name_check(known_net, inst_conn, net_alias, mod): - return True - elif inst_conn.lower() == known_net.lower() and subinst.mod not in mod_set: - if subinst.mod.is_net_alias(mod_pin, net_alias, mod, exclusion_set): - return True - mod_set.add(subinst.mod) - return False - - def is_net_alias_name_check(self, parent_net, child_net, alias_net, mod): - """Utility function for checking single net alias.""" - return self == mod and \ - child_net.lower() == alias_net.lower() and \ - parent_net.lower() == alias_net.lower() - def translate_nets(self, subinst_ports, port_dict, inst_name): """Converts connection names to their spice hierarchy equivalent""" converted_conns = [] diff --git a/compiler/base/hierarchy_spice.py b/compiler/base/hierarchy_spice.py index 5a15fce5..c436d260 100644 --- a/compiler/base/hierarchy_spice.py +++ b/compiler/base/hierarchy_spice.py @@ -490,3 +490,48 @@ class spice(): def return_power(self, dynamic=0.0, leakage=0.0): return power_data(dynamic, leakage) + def find_aliases(self, inst_name, port_nets, path_nets, alias, alias_mod, exclusion_set=None): + """Given a list of nets, will compare the internal alias of a mod to determine + if the nets have a connection to this mod's net (but not inst). + """ + if not exclusion_set: + exclusion_set = set() + try: + self.name_dict + except AttributeError: + self.name_dict = {} + self.build_names(self.name_dict, inst_name, port_nets) + aliases = [] + for net in path_nets: + net = net.lower() + int_net = self.name_dict[net]['int_net'] + int_mod = self.name_dict[net]['mod'] + if int_mod.is_net_alias(int_net, alias, alias_mod, exclusion_set): + aliases.append(net) + return aliases + + def is_net_alias(self, known_net, net_alias, mod, exclusion_set): + """Checks if the alias_net in input mod is the same as the input net for this mod (self).""" + if self in exclusion_set: + return False + # Check ports of this mod + for pin in self.pins: + if self.is_net_alias_name_check(known_net, pin, net_alias, mod): + return True + # Check connections of all other subinsts + mod_set = set() + for subinst, inst_conns in zip(self.insts, self.conns): + for inst_conn, mod_pin in zip(inst_conns, subinst.mod.pins): + if self.is_net_alias_name_check(known_net, inst_conn, net_alias, mod): + return True + elif inst_conn.lower() == known_net.lower() and subinst.mod not in mod_set: + if subinst.mod.is_net_alias(mod_pin, net_alias, mod, exclusion_set): + return True + mod_set.add(subinst.mod) + return False + + def is_net_alias_name_check(self, parent_net, child_net, alias_net, mod): + """Utility function for checking single net alias.""" + return self == mod and \ + child_net.lower() == alias_net.lower() and \ + parent_net.lower() == alias_net.lower() From d027632bdc7a9164acb6f98688a1fedc2d528e95 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Wed, 2 Sep 2020 14:22:18 -0700 Subject: [PATCH 29/31] Moved majority of code duplicated between delay and functional to simulation --- compiler/characterizer/delay.py | 97 +--------------------------- compiler/characterizer/functional.py | 63 +----------------- compiler/characterizer/simulation.py | 93 ++++++++++++++++++++++++++ 3 files changed, 95 insertions(+), 158 deletions(-) diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index 556e02bb..f04965e5 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -252,18 +252,7 @@ class delay(simulation): self.load = load self.slew = slew - - def add_graph_exclusions(self): - """Exclude portions of SRAM from timing graph which are not relevant""" - - # other initializations can only be done during analysis when a bit has been selected - # for testing. - self.sram.bank.graph_exclude_precharge() - self.sram.graph_exclude_addr_dff() - self.sram.graph_exclude_data_dff() - self.sram.graph_exclude_ctrl_dffs() - self.sram.bank.bitcell_array.graph_exclude_replica_col_bits() - + def create_graph(self): """Creates timing graph to generate the timing paths for the SRAM output.""" @@ -275,90 +264,6 @@ class delay(simulation): self.sram_spc_name = "X{}".format(self.sram.name) self.sram.build_graph(self.graph,self.sram_spc_name,self.pins) - def set_internal_spice_names(self): - """Sets important names for characterization such as Sense amp enable and internal bit nets.""" - - port = self.read_ports[0] - if not OPTS.use_pex: - self.graph.get_all_paths('{}{}'.format("clk", port), - '{}{}_{}'.format(self.dout_name, port, self.probe_data)) - - sen_with_port = self.get_sen_name(self.graph.all_paths) - if sen_with_port.endswith(str(port)): - self.sen_name = sen_with_port[:-len(str(port))] - else: - self.sen_name = sen_with_port - debug.warning("Error occurred while determining SEN name. Can cause faults in simulation.") - - debug.info(2,"s_en name = {}".format(self.sen_name)) - - bl_name_port, br_name_port = self.get_bl_name(self.graph.all_paths, port) - port_pos = -1-len(str(self.probe_data))-len(str(port)) - - if bl_name_port.endswith(str(port)+"_"+str(self.probe_data)): - self.bl_name = bl_name_port[:port_pos] +"{}"+ bl_name_port[port_pos+len(str(port)):] - elif not bl_name_port[port_pos].isdigit(): # single port SRAM case, bl will not be numbered eg bl_0 - self.bl_name = bl_name_port - else: - self.bl_name = bl_name_port - debug.warning("Error occurred while determining bitline names. Can cause faults in simulation.") - - if br_name_port.endswith(str(port)+"_"+str(self.probe_data)): - self.br_name = br_name_port[:port_pos] +"{}"+ br_name_port[port_pos+len(str(port)):] - elif not br_name_port[port_pos].isdigit(): # single port SRAM case, bl will not be numbered eg bl_0 - self.br_name = br_name_port - else: - self.br_name = br_name_port - debug.warning("Error occurred while determining bitline names. Can cause faults in simulation.") - debug.info(2,"bl name={}, br name={}".format(self.bl_name,self.br_name)) - else: - self.graph.get_all_paths('{}{}'.format("clk", port), - '{}{}_{}'.format(self.dout_name, port, self.probe_data)) - - self.sen_name = self.get_sen_name(self.graph.all_paths) - debug.info(2,"s_en name = {}".format(self.sen_name)) - - - self.bl_name = "bl{0}_{1}".format(port, OPTS.word_size-1) - self.br_name = "br{0}_{1}".format(port, OPTS.word_size-1) - debug.info(2,"bl name={}, br name={}".format(self.bl_name,self.br_name)) - - - def get_sen_name(self, paths, assumed_port=None): - """ - Gets the signal name associated with the sense amp enable from input paths. - Only expects a single path to contain the sen signal name. - """ - - sa_mods = factory.get_mods(OPTS.sense_amp) - # Any sense amp instantiated should be identical, any change to that - # will require some identification to determine the mod desired. - debug.check(len(sa_mods) == 1, "Only expected one type of Sense Amp. Cannot perform s_en checks.") - enable_name = sa_mods[0].get_enable_name() - sen_name = self.get_alias_in_path(paths, enable_name, sa_mods[0]) - if OPTS.use_pex: - sen_name = sen_name.split('.')[-1] - return sen_name - - def get_bl_name(self, paths, port): - """Gets the signal name associated with the bitlines in the bank.""" - - cell_mod = factory.create(module_type=OPTS.bitcell) - cell_bl = cell_mod.get_bl_name(port) - cell_br = cell_mod.get_br_name(port) - - bl_found = False - # Only a single path should contain a single s_en name. Anything else is an error. - bl_names = [] - exclude_set = self.get_bl_name_search_exclusions() - for int_net in [cell_bl, cell_br]: - bl_names.append(self.get_alias_in_path(paths, int_net, cell_mod, exclude_set)) - if OPTS.use_pex: - for i in range(len(bl_names)): - bl_names[i] = bl_names[i].split('.')[-1] - return bl_names[0], bl_names[1] - - def get_bl_name_search_exclusions(self): """Gets the mods as a set which should be excluded while searching for name.""" diff --git a/compiler/characterizer/functional.py b/compiler/characterizer/functional.py index 8574c4f6..67e0d224 100644 --- a/compiler/characterizer/functional.py +++ b/compiler/characterizer/functional.py @@ -419,18 +419,6 @@ class functional(simulation): self.stim.write_control(self.cycle_times[-1] + self.period) self.sf.close() - - # FIXME: refactor to share with delay.py - def add_graph_exclusions(self): - """Exclude portions of SRAM from timing graph which are not relevant""" - - # other initializations can only be done during analysis when a bit has been selected - # for testing. - self.sram.bank.graph_exclude_precharge() - self.sram.graph_exclude_addr_dff() - self.sram.graph_exclude_data_dff() - self.sram.graph_exclude_ctrl_dffs() - self.sram.bank.bitcell_array.graph_exclude_replica_col_bits() # FIXME: refactor to share with delay.py def create_graph(self): @@ -444,25 +432,7 @@ class functional(simulation): self.graph = graph_util.timing_graph() self.sram_spc_name = "X{}".format(self.sram.name) self.sram.build_graph(self.graph, self.sram_spc_name, self.pins) - - # FIXME: refactor to share with delay.py - def set_internal_spice_names(self): - """Sets important names for characterization such as Sense amp enable and internal bit nets.""" - - # For now, only testing these using first read port. - port = self.read_ports[0] - self.graph.get_all_paths('{}{}'.format("clk", port), - '{}{}_{}'.format(self.dout_name, port, 0).lower()) - - self.sen_name = self.get_sen_name(self.graph.all_paths) - debug.info(2, "s_en name = {}".format(self.sen_name)) - - self.bl_name, self.br_name = self.get_bl_name(self.graph.all_paths, port) - debug.info(2, "bl name={}, br name={}".format(self.bl_name, self.br_name)) - - self.q_name, self.qbar_name = self.get_bit_name() - debug.info(2, "q name={}\nqbar name={}".format(self.q_name, self.qbar_name)) - + def get_bit_name(self): """ Get a bit cell name """ (cell_name, cell_inst) = self.sram.get_cell_name(self.sram.name, 0, 0) @@ -473,37 +443,6 @@ class functional(simulation): qbar_name = cell_name + '.' + str(storage_names[1]) return (q_name, qbar_name) - - # FIXME: refactor to share with delay.py - def get_sen_name(self, paths): - """ - Gets the signal name associated with the sense amp enable from input paths. - Only expects a single path to contain the sen signal name. - """ - - sa_mods = factory.get_mods(OPTS.sense_amp) - # Any sense amp instantiated should be identical, any change to that - # will require some identification to determine the mod desired. - debug.check(len(sa_mods) == 1, "Only expected one type of Sense Amp. Cannot perform s_en checks.") - enable_name = sa_mods[0].get_enable_name() - sen_name = self.get_alias_in_path(paths, enable_name, sa_mods[0]) - return sen_name - - # FIXME: refactor to share with delay.py - def get_bl_name(self, paths, port): - """Gets the signal name associated with the bitlines in the bank.""" - - cell_mod = factory.create(module_type=OPTS.bitcell) - cell_bl = cell_mod.get_bl_name(port) - cell_br = cell_mod.get_br_name(port) - - # Only a single path should contain a single s_en name. Anything else is an error. - bl_names = [] - exclude_set = self.get_bl_name_search_exclusions() - for int_net in [cell_bl, cell_br]: - bl_names.append(self.get_alias_in_path(paths, int_net, cell_mod, exclude_set)) - - return bl_names[0], bl_names[1] def get_bl_name_search_exclusions(self): """Gets the mods as a set which should be excluded while searching for name.""" diff --git a/compiler/characterizer/simulation.py b/compiler/characterizer/simulation.py index 064eb2c5..9768e241 100644 --- a/compiler/characterizer/simulation.py +++ b/compiler/characterizer/simulation.py @@ -408,3 +408,96 @@ class simulation(): pin_names.append("{0}".format("gnd")) return pin_names + def add_graph_exclusions(self): + """Exclude portions of SRAM from timing graph which are not relevant""" + + # other initializations can only be done during analysis when a bit has been selected + # for testing. + self.sram.bank.graph_exclude_precharge() + self.sram.graph_exclude_addr_dff() + self.sram.graph_exclude_data_dff() + self.sram.graph_exclude_ctrl_dffs() + self.sram.bank.bitcell_array.graph_exclude_replica_col_bits() + + def set_internal_spice_names(self): + """Sets important names for characterization such as Sense amp enable and internal bit nets.""" + + port = self.read_ports[0] + if not OPTS.use_pex: + self.graph.get_all_paths('{}{}'.format("clk", port), + '{}{}_{}'.format(self.dout_name, port, self.probe_data)) + + sen_with_port = self.get_sen_name(self.graph.all_paths) + if sen_with_port.endswith(str(port)): + self.sen_name = sen_with_port[:-len(str(port))] + else: + self.sen_name = sen_with_port + debug.warning("Error occurred while determining SEN name. Can cause faults in simulation.") + + debug.info(2,"s_en name = {}".format(self.sen_name)) + + bl_name_port, br_name_port = self.get_bl_name(self.graph.all_paths, port) + port_pos = -1-len(str(self.probe_data))-len(str(port)) + + if bl_name_port.endswith(str(port)+"_"+str(self.probe_data)): + self.bl_name = bl_name_port[:port_pos] +"{}"+ bl_name_port[port_pos+len(str(port)):] + elif not bl_name_port[port_pos].isdigit(): # single port SRAM case, bl will not be numbered eg bl_0 + self.bl_name = bl_name_port + else: + self.bl_name = bl_name_port + debug.warning("Error occurred while determining bitline names. Can cause faults in simulation.") + + if br_name_port.endswith(str(port)+"_"+str(self.probe_data)): + self.br_name = br_name_port[:port_pos] +"{}"+ br_name_port[port_pos+len(str(port)):] + elif not br_name_port[port_pos].isdigit(): # single port SRAM case, bl will not be numbered eg bl_0 + self.br_name = br_name_port + else: + self.br_name = br_name_port + debug.warning("Error occurred while determining bitline names. Can cause faults in simulation.") + debug.info(2,"bl name={}, br name={}".format(self.bl_name,self.br_name)) + else: + self.graph.get_all_paths('{}{}'.format("clk", port), + '{}{}_{}'.format(self.dout_name, port, self.probe_data)) + + self.sen_name = self.get_sen_name(self.graph.all_paths) + debug.info(2,"s_en name = {}".format(self.sen_name)) + + + self.bl_name = "bl{0}_{1}".format(port, OPTS.word_size-1) + self.br_name = "br{0}_{1}".format(port, OPTS.word_size-1) + debug.info(2,"bl name={}, br name={}".format(self.bl_name,self.br_name)) + + def get_sen_name(self, paths, assumed_port=None): + """ + Gets the signal name associated with the sense amp enable from input paths. + Only expects a single path to contain the sen signal name. + """ + + sa_mods = factory.get_mods(OPTS.sense_amp) + # Any sense amp instantiated should be identical, any change to that + # will require some identification to determine the mod desired. + debug.check(len(sa_mods) == 1, "Only expected one type of Sense Amp. Cannot perform s_en checks.") + enable_name = sa_mods[0].get_enable_name() + sen_name = self.get_alias_in_path(paths, enable_name, sa_mods[0]) + if OPTS.use_pex: + sen_name = sen_name.split('.')[-1] + return sen_name + + + def get_bl_name(self, paths, port): + """Gets the signal name associated with the bitlines in the bank.""" + + cell_mod = factory.create(module_type=OPTS.bitcell) + cell_bl = cell_mod.get_bl_name(port) + cell_br = cell_mod.get_br_name(port) + + bl_found = False + # Only a single path should contain a single s_en name. Anything else is an error. + bl_names = [] + exclude_set = self.get_bl_name_search_exclusions() + for int_net in [cell_bl, cell_br]: + bl_names.append(self.get_alias_in_path(paths, int_net, cell_mod, exclude_set)) + if OPTS.use_pex: + for i in range(len(bl_names)): + bl_names[i] = bl_names[i].split('.')[-1] + return bl_names[0], bl_names[1] \ No newline at end of file From 500327d59ba077d38932699171bd034972315d42 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Fri, 4 Sep 2020 02:24:18 -0700 Subject: [PATCH 30/31] Fixed import in simulation and fixed names in functional --- compiler/characterizer/functional.py | 4 ++++ compiler/characterizer/simulation.py | 1 + 2 files changed, 5 insertions(+) diff --git a/compiler/characterizer/functional.py b/compiler/characterizer/functional.py index 67e0d224..395c612b 100644 --- a/compiler/characterizer/functional.py +++ b/compiler/characterizer/functional.py @@ -38,6 +38,7 @@ class functional(simulation): if not self.num_spare_cols: self.num_spare_cols = 0 + self.probe_address, self.probe_data = '0'*self.addr_size,0 self.set_corner(corner) self.set_spice_constants() self.set_stimulus_variables() @@ -47,6 +48,8 @@ class functional(simulation): self.add_graph_exclusions() self.create_graph() self.set_internal_spice_names() + self.q_name, self.qbar_name = self.get_bit_name() + debug.info(2, "q name={}\nqbar name={}".format(self.q_name, self.qbar_name)) # Number of checks can be changed self.num_cycles = 15 @@ -433,6 +436,7 @@ class functional(simulation): self.sram_spc_name = "X{}".format(self.sram.name) self.sram.build_graph(self.graph, self.sram_spc_name, self.pins) + #FIXME: Similar function to delay.py, refactor this def get_bit_name(self): """ Get a bit cell name """ (cell_name, cell_inst) = self.sram.get_cell_name(self.sram.name, 0, 0) diff --git a/compiler/characterizer/simulation.py b/compiler/characterizer/simulation.py index 9768e241..b73af4f6 100644 --- a/compiler/characterizer/simulation.py +++ b/compiler/characterizer/simulation.py @@ -15,6 +15,7 @@ from .trim_spice import * from .charutils import * import utils from globals import OPTS +from sram_factory import factory class simulation(): From af22e438f121853d878021a55ff3e810f522198e Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Tue, 8 Sep 2020 18:40:39 -0700 Subject: [PATCH 31/31] Added option to output an extended configuration file that includes defaults. --- compiler/options.py | 2 ++ compiler/sram/sram.py | 20 ++++++++++++++++++++ 2 files changed, 22 insertions(+) diff --git a/compiler/options.py b/compiler/options.py index d97ea300..8d8e3b42 100644 --- a/compiler/options.py +++ b/compiler/options.py @@ -93,6 +93,8 @@ class options(optparse.Values): trim_netlist = False # Run with extracted parasitics use_pex = False + # Output config with all options + output_extended_config = False ################### diff --git a/compiler/sram/sram.py b/compiler/sram/sram.py index 8cf926c6..6b5d117d 100644 --- a/compiler/sram/sram.py +++ b/compiler/sram/sram.py @@ -63,6 +63,18 @@ class sram(): def verilog_write(self, name): self.s.verilog_write(name) + def extended_config_write(self, name): + """Dump config file with all options. + Include defaults and anything changed by input config.""" + f = open(name, "w") + var_dict = dict((name, getattr(OPTS, name)) for name in dir(OPTS) if not name.startswith('__') and not callable(getattr(OPTS, name))) + for var_name, var_value in var_dict.items(): + if isinstance(var_value, str): + f.write(str(var_name) + " = " + "\"" + str(var_value) + "\"\n") + else: + f.write(str(var_name) + " = " + str(var_value)+ "\n") + f.close() + def save(self): """ Save all the output files while reporting time to do it as well. """ @@ -137,3 +149,11 @@ class sram(): debug.print_raw("Verilog: Writing to {0}".format(vname)) self.verilog_write(vname) print_time("Verilog", datetime.datetime.now(), start_time) + + # Write out options if specified + if OPTS.output_extended_config: + start_time = datetime.datetime.now() + oname = OPTS.output_path + OPTS.output_name + "_extended.py" + debug.print_raw("Extended Config: Writing to {0}".format(oname)) + self.extended_config_write(oname) + print_time("Extended Config", datetime.datetime.now(), start_time) \ No newline at end of file