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Merge branch 'dev' into wlbuffer

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mrg
2020-09-10 13:05:14 -07:00
parent f2313d0c73 af22e438f1
commit 71d86f88b0
63 changed files with 639 additions and 935 deletions
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compiler/modules/bitcell_array.py
-7
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@@ -104,13 +104,6 @@ class bitcell_array(bitcell_base_array):
bl_wire.wire_c =spice["min_tx_drain_c"] + bl_wire.wire_c
return bl_wire
def get_wordline_cin(self):
"""Get the relative input capacitance from the wordline connections in all the bitcell"""
# A single wordline is connected to all the bitcells in a single row meaning the capacitance depends on the # of columns
bitcell_wl_cin = self.cell.get_wl_cin()
total_cin = bitcell_wl_cin * self.column_size
return total_cin
def graph_exclude_bits(self, targ_row, targ_col):
"""Excludes bits in column from being added to graph except target"""
# Function is not robust with column mux configurations