mirror of https://github.com/VLSIDA/OpenRAM.git
Remove unused contact in pnand3
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parent
0ee6963198
commit
717cbb0fe5
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@ -69,14 +69,34 @@ class pnand3(pgate.pgate):
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def add_ptx(self):
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def add_ptx(self):
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""" Create the PMOS and NMOS transistors. """
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""" Create the PMOS and NMOS transistors. """
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self.nmos = factory.create(module_type="ptx",
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self.nmos_nsnd = factory.create(module_type="ptx",
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width=self.nmos_width,
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width=self.nmos_width,
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mults=self.tx_mults,
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mults=self.tx_mults,
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tx_type="nmos",
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tx_type="nmos",
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connect_poly=True,
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add_source_contact=False,
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connect_active=True)
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add_drain_contact=False,
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self.add_mod(self.nmos)
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connect_poly=True,
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connect_active=True)
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self.add_mod(self.nmos_nsnd)
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self.nmos_ns = factory.create(module_type="ptx",
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width=self.nmos_width,
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mults=self.tx_mults,
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tx_type="nmos",
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add_source_contact=False,
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connect_poly=True,
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connect_active=True)
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self.add_mod(self.nmos_ns)
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self.nmos_nd = factory.create(module_type="ptx",
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width=self.nmos_width,
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mults=self.tx_mults,
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tx_type="nmos",
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add_drain_contact=False,
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connect_poly=True,
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connect_active=True)
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self.add_mod(self.nmos_nd)
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self.pmos = factory.create(module_type="ptx",
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self.pmos = factory.create(module_type="ptx",
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width=self.pmos_width,
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width=self.pmos_width,
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mults=self.tx_mults,
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mults=self.tx_mults,
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@ -130,15 +150,15 @@ class pnand3(pgate.pgate):
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self.connect_inst(["Z", "C", "vdd", "vdd"])
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self.connect_inst(["Z", "C", "vdd", "vdd"])
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self.nmos1_inst = self.add_inst(name="pnand3_nmos1",
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self.nmos1_inst = self.add_inst(name="pnand3_nmos1",
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mod=self.nmos)
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mod=self.nmos_nd)
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self.connect_inst(["Z", "C", "net1", "gnd"])
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self.connect_inst(["Z", "C", "net1", "gnd"])
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self.nmos2_inst = self.add_inst(name="pnand3_nmos2",
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self.nmos2_inst = self.add_inst(name="pnand3_nmos2",
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mod=self.nmos)
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mod=self.nmos_nsnd)
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self.connect_inst(["net1", "B", "net2", "gnd"])
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self.connect_inst(["net1", "B", "net2", "gnd"])
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self.nmos3_inst = self.add_inst(name="pnand3_nmos3",
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self.nmos3_inst = self.add_inst(name="pnand3_nmos3",
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mod=self.nmos)
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mod=self.nmos_ns)
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self.connect_inst(["net2", "A", "gnd", "gnd"])
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self.connect_inst(["net2", "A", "gnd", "gnd"])
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def place_ptx(self):
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def place_ptx(self):
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@ -171,7 +191,7 @@ class pnand3(pgate.pgate):
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""" Add n/p well taps to the layout and connect to supplies """
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""" Add n/p well taps to the layout and connect to supplies """
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self.add_nwell_contact(self.pmos, self.pmos3_pos)
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self.add_nwell_contact(self.pmos, self.pmos3_pos)
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self.add_pwell_contact(self.nmos, self.nmos3_pos)
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self.add_pwell_contact(self.nmos_ns, self.nmos3_pos)
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def connect_rails(self):
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def connect_rails(self):
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""" Connect the nmos and pmos to its respective power rails """
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""" Connect the nmos and pmos to its respective power rails """
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@ -259,7 +279,7 @@ class pnand3(pgate.pgate):
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# In fF
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# In fF
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c_para = spice["min_tx_drain_c"] * (self.nmos_size / parameter["min_tx_size"])
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c_para = spice["min_tx_drain_c"] * (self.nmos_size / parameter["min_tx_size"])
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transition_prob = 0.1094
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transition_prob = 0.1094
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return transition_prob * (c_load + c_para)
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return transition_prob * (c_load + c_para)
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def input_load(self):
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def input_load(self):
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"""Return the relative input capacitance of a single input"""
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"""Return the relative input capacitance of a single input"""
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