diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py
index 8dbcfaf4..f9a40545 100644
--- a/compiler/sram/sram_1bank.py
+++ b/compiler/sram/sram_1bank.py
@@ -320,7 +320,9 @@ class sram_1bank(sram_base):
             # Only input (besides pins) is the replica bitline
             src_pin = self.control_logic_insts[port].get_pin("rbl_bl")
             dest_pin = self.bank_inst.get_pin("rbl_bl{}".format(port))
-            self.connect_hbus(src_pin, dest_pin)
+            self.add_wire(self.m2_stack[::-1],
+                          [src_pin.center(), vector(src_pin.cx(), dest_pin.cy()), dest_pin.rc()])
+            # self.connect_hbus(src_pin, dest_pin)
             
     def route_row_addr_dff(self):
         """ Connect the output of the row flops to the bank pins """